74AC109 ,Dual JK Positive Edge-Triggered Flip-Flop54AC/74AC109 54ACT/74ACT109DualJKPositiveEdge-TriggeredFlip-Flop#February199354AC/74AC109 54ACT/74A ..
74AC109MTCX ,Dual JK Positive Edge-Triggered Flip-FlopFeaturesThe AC/ACT109 consists of two high-speed completely
74AC109
Dual JK Positive Edge-Triggered Flip-Flop
TL/F/9923
54AC/74AC109
54ACT/74ACT109
Dual
Positive
Edge-Triggered
Flip-Flop
February 1993
54AC/74AC109# 54ACT/74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consistsoftwo high-speed completely
independent transition clockedJK flip-flops. The clocking
operationis independentofrise andfall timesofthe clock
waveform. TheJK design allows operationasaD flip-flop
(referto ’AC/’ACT74 data sheet)by connectingtheJandK
inputs together.
Asynchronous Inputs:
LOW inputtoSD (Set) setsQto HIGH level
LOW inputtoCD (Clear) setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQandQ
HIGH
Features ICC reducedby 50% Outputs source/sink24mA ’ACT109has TTL-compatible inputs Standard Military Drawing (SMD) ’AC109: 5962-89551 ’ACT109: 5962-88534
Logic Symbols
TL/F/9923–1
IEEE/IEC
TL/F/9923–7
Pin Names Description
J1,J2,K1,K2 Data Inputs
CP1,CP2 Clock Pulse Inputs
CD1,CD2 DirectClear Inputs
SD1,SD2 DirectSet Inputs
Q1,Q2,Q1,Q2 Outputs
TL/F/9923–2
Connection Diagrams
PinAssignment
for DIP, Flatpakand SOIC
TL/F/9923–3
PinAssignment
for LCC
TL/F/9923–4
FACTTMisa trademarkof NationalSemiconductor Corporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
