74ABT541CSJX ,Octal Buffer/Line Driver with 3-STATE OutputsElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
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74FCT244 , FCT Interface Logic Octal Buffers/Line Drivers, Three-State
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74ABT541CMSAX-74ABT541CMTC-74ABT541CMTCX-74ABT541CSC-74ABT541CSCX-74ABT541CSJ-74ABT541CSJX
Octal Buffer/Line Driver with 3-STATE Outputs
74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs September 1992 Revised March 2005 74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The ABT541 is an octal buffer and line driver with 3-STATENon-inverting buffers outputs designed to be employed as a memory andOutput sink capability of 64 mA, source capability of address driver, clock driver, or bus-oriented transmitter/ 32 mA receiver. The ABT541 is similar to the ABT244 with broad- Guaranteed output skew side pinout. Guaranteed multiple output switching specifications Output switching specified for both 50 pF and 250 pF loads Guaranteed simultaneous switching, noise level and dynamic threshold performance Guaranteed latchup protection High impedance, glitch free bus loading during entire power up and power down cycle Nondestructive hot insertion capability Flow-through pinout for ease of PC board layout Disable time less than enable time to avoid bus contention Ordering Code: Order Number Package Number Package Description 74ABT541CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ABT541CSJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT541CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT541CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT541CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names Description OE , OE Output Enable Input (Active LOW) 1 2 I –I Inputs 0 7 O –O Outputs 0 7 Truth Table Inputs Outputs OE OE I 1 2 LL H H HX X Z XHX Z LLL L H HIGH Voltage Level X Immaterial L LOW Voltage Level Z High Impedance © 2005 DS011501
