74ABT373ADB ,Octal transparent latch 3-StateINTEGRATED CIRCUITS74ABT373AOctal transparent latch (3-State)Product specification 1995 Feb 17IC23 ..
74ABT373APW ,Octal transparent latch (3-State)FEATURES DESCRIPTIONThe 74ABT373A high-performance BiCMOS device combines low• 8-bit transparent l ..
74ABT373CMSA ,Octal Transparent Latch with 3-STATE Outputsapplications. The flip-flops
74ABT373AD-74ABT373ADB-74ABT373APW
Octal transparent latch 3-State
Product specification 1995 Feb 17
IC23 Data Handbook
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
FEATURES 8-bit transparent latch 3-State output buffers Output capability: +64mA/–32mA Latch-up protection exceeds 500mA per JEDEC Std 17 ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model Power-up 3-State Power-up reset Live insertion/extraction permitted
DESCRIPTIONThe 74ABT373A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT373A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE)
control gates.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
LOGIC SYMBOL
FUNCTION TABLE= High voltage level= High voltage level one set-up time prior to the High-to-Low E
transition= Low voltage level = Low voltage level one set-up time prior to the High-to-Low E
transition
NC= No change= Don’t care= High impedance “off” state= High-to-Low E transition
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
DC ELECTRICAL CHARACTERISTICS
NOTES: Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4V. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICSGND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
Philips Semiconductors Product specification
74ABT373AOctal transparent latch (3-State)
AC SETUP REQUIREMENTSGND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
AC WAVEFORMSVM = 1.5V, VIN = GND to 3.0V
Waveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
Waveform 2. Propagation Delay for Data to Outputs
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
