74ABT273CMTCX ,Octal D-Type Flip-FlopFeaturesThe ABT273 has eight edge-triggered D-type flip-flops with
74ABT273CMSA-74ABT273CMTC-74ABT273CMTCX-74ABT273CSC-74ABT273CSCX
Octal D-Type Flip-Flop
74ABT273 Octal D-Type Flip-Flop January 1993 Revised March 2005 74ABT273 Octal D-Type Flip-Flop General Description Features The ABT273 has eight edge-triggered D-type flip-flops withEight edge-triggered D-type flip-flops individual D inputs and Q outputs. The common bufferedBuffered common clock Clock (CP) and Master Reset (MR) inputs load and reset Buffered, asynchronous Master Reset (clear) all flip-flops simultaneously. See ABT377 for clock enable version The register is fully edge-triggered. The state of each D See ABT373 for transparent latch version input, one setup time before the LOW-to-HIGH clock transi- See ABT374 for 3-STATE version tion, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock orOutput sink capability of 64 mA, source capability of 32 mA Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output onlyGuaranteed latchup protection is required and the Clock and Master Reset are common to High impedance glitch free bus loading during entire all storage elements. power up and power down cycle Non-destructive hot insertion capability Disable time less than enable time to avoid bus conten- tion Ordering Code: Package Order Number Package Description Number 74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ABT273CSJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT273CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT273CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT273CMTCX_NL MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Pin Descriptions Pin Names Description D –D Data Inputs 0 7 MR Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) Q –Q Data Outputs 0 7 © 2005 DS011549
