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74ABT16823-74ABT16823ADGG-74ABT16823ADL
18-bit bus interface D-type flip-flop with reset and enable 3-State
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Philips Semiconductors Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
FEATURES Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors Live insertion/extraction permitted Power-up 3-State 74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs Power-up Reset Output capability: +64mA/–32mA Latch-up protection exceeds 500mA per Jedec Std 17 ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTIONThe 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
Philips Semiconductors Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
LOGIC DIAGRAM
FUNCTION TABLE= High voltage level= High voltage level one set-up time prior to the Low-to-High clock transition= Low voltage level = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change= Don’t care= High impedance “off” state= Low to High clock transition= Not a Low-to-High clock transition
Philips Semiconductors Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74ABT16823A
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
DC ELECTRICAL CHARACTERISTICS
NOTES: Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4V. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100μsec is permitted. This is the bus hold overdrive current required to force the input to the opposite logic state.
