74ABT16543CMTD ,16-Bit Registered Transceiver with 3-STATE OutputsFunctional DescriptionThe ABT16543 contains two sets of D-type latches, with mode and their outputs ..
74ABT16543CMTDX ,16-Bit Registered Transceiver with 3-STATE Outputs74ABT16543 16-Bit Registered Transceiver with 3-STATE OutputsOctober 1993Revised January 199974ABT1 ..
74ABT16543DL ,16-bit latched transceivers with dual enable 3-State
74ABT16543DL ,16-bit latched transceivers with dual enable 3-State
74ABT16543DL ,16-bit latched transceivers with dual enable 3-State
74ABT16543DL ,16-bit latched transceivers with dual enable 3-State
74F86SJ ,2-Input Exclusive-OR GateGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic exc ..
74F86SJX ,2-Input Exclusive-OR GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74F899 ,9-Bit Latchable Transceiver with Parity Generator/Checkerapplications in place of the74F657 and 74F373 (no need to change T/R to checkparity) Ordering Code: ..
74f899 ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QC ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QCX ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74ABT16543CMTD-74ABT16543CMTDX
16-Bit Registered Transceiver with 3-STATE Outputs
74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs October 1993 Revised January 1999 74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features The ABT16543 16-bit transceiver contains two sets of D- � Back-to-back registers for storage type latches for temporary storage of data flowing in either � Bidirectional data path direction. Separate Latch Enable and Output Enable inputs � A and B outputs have current sourcing capability of 32 are provided for each register to permit independent con- mA and current sinking capability of 64 mA trol of inputting and outputting in either direction of data � Separate control logic for each byte flow. Each byte has separate control inputs, which can be � 16-bit version of the ABT543 shorted together for full 16-bit operation. � Separate controls for data flow in each direction � Guaranteed latchup protection � High impedance glitch free bus loading during entire power up and power down cycle � Nondestructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT16543CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16543CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) n OEBA B-to-A Output Enable Input (Active LOW) n CEAB A-to-B Enable Input (Active LOW) n CEBA B-to-A Enable Input (Active LOW) n LEAB A-to-B Latch Enable Input (Active LOW) n LEBA B-to-A Latch Enable Input (Active LOW) n A –A A-to-B Data Inputs or 0 15 B-to-A 3-STATE Outputs B –B B-to-A Data Inputs or 0 15 A-to-B 3-STATE Outputs © 1999 DS011646.prf
