74ABT16500 ,18-Bit Universal Bus Transceivers with 3-STATE OutputsFeaturesclock (CLKAB and CLKBA) inputs. For A-to-B data flow, thedevice operates in the transparent ..
74ABT16500C ,18-bit universal bus transceiver (3-State)
74ABT16500CMTDX ,18-Bit Registered Bus Transceiver with 3-STATE OutputsFeaturesclock (CLKAB and CLKBA) inputs. For A-to-B data flow, thedevice operates in the transparent ..
74ABT16501 ,18-Bit Universal Bus Transceivers with 3-STATE Outputs
74ABT16501 ,18-Bit Universal Bus Transceivers with 3-STATE OutputsFeaturesdevice operates in the transparent mode when LEAB isHIGH. When LEAB is LOW, the A data is l ..
74ABT16501CMTD ,18-Bit Universal Bus Transceivers with 3-STATE OutputsGeneral DescriptionLOW).The ABT16501 18-bit universal bus transceiver combinesTo ensure the high-im ..
74F86PC ,2-Input Exclusive-OR GateGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic exc ..
74F86SC ,2-Input Exclusive-OR GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74F86SC ,2-Input Exclusive-OR Gate74F86 2-Input Exclusive-OR GateApril 1988Revised June 200374F862-Input Exclusive-OR Gate
74F86SCX ,2-Input Exclusive-OR GateGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic exc ..
74F86SJ ,2-Input Exclusive-OR GateGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic exc ..
74F86SJX ,2-Input Exclusive-OR GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74ABT16500
18-Bit Universal Bus Transceivers with 3-STATE Outputs
74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs April 1993 Revised January 1999 74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs plementary (OEAB is active HIGH and OEBA is active General Description LOW). To ensure the high-impedance state during power up or The ABT16500 18-bit universal bus transceiver combines power down, OE should be tied to GND through a pulldown D-type latches and D-type flip-flops to allow data flow in resistor; the minimum value of the resistor is determined by transparent, latched, and clocked modes. the current-sourcing capability of the driver. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and Features clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is � Combines D-Type latches and D-Type flip-flops for HIGH. When LEAB is LOW, the A data is latched if CLKAB operation in transparent, latched, or clocked mode is held at a HIGH or LOW logic level. If LEAB is LOW, the A � Flow-through architecture optimizes PCB layout bus data is stored in the latch/flip-flop on the HIGH-to-LOW � Guaranteed latch-up protection transition of CLKAB. Output-enable OEAB is active-high. � High impedance glitch free bus loading during entire When OEAB is HIGH, the outputs are active. When OEAB power up and power down cycle is LOW, the outputs are in the high-impedance state. � Non-destructive hot insertion capability Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are com- Ordering Code: Order Number Package Number Package Description 74ABT16500CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16500CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Connection Diagram Function Table (Note 1) Inputs Output Pin Assignment for SSOP OEAB LEAB CLKABAB L XXX Z HH X L L HH X H H HL ↓ LL HL ↓ HH HL H X B (Note 2) 0 HL L X B (Note 3) 0 Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. © 1999 DS011581.prf
