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7473NSN/a37avaiDual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs


7473 ,Dual Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral Descriptiontransferred to the slave. The logic states of the J and KThis device contains tw ..
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7473
Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs September 1986 Revised February 2000 DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs negative transition of the clock, the data from the master is General Description transferred to the slave. The logic states of the J and K This device contains two independent positive pulse trig- inputs must not be allowed to change while the clock is gered J-K flip-flops with complementary outputs. The J and HIGH. Data transfers to the outputs on the falling edge of K data is processed by the flip-flops after a complete clock the clock pulse. A LOW logic level on the clear input will pulse. While the clock is LOW the slave is isolated from the reset the outputs regardless of the logic states of the other master. On the positive transition of the clock, the data inputs. from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the Ordering Code: Order Number Package Number Package Description DM7473N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Inputs Outputs CLR CLK J K Q Q LX X X L H HLL Q Q 0 0 HHL H L HLH L H HH H Toggle H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Positive pulse data. the J and K inputs must be held constant while the clock is HIGH. Data is transferred to the outputs on the falling edge of the clock pulse. Q = The output logic level before the indicated input conditions were 0 established. Toggle = Each output changes to the complement of its previous level on each HIGH level clock pulse. © 2000 DS006525
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