7438SJ ,Quad 2-Input NAND Buffers with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
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74F569SJ ,4-Bit Bidirectional Counter with 3-STATE OutputsFunctional DescriptionThe 74F569 counts in the modulo-16 binary sequence. stage counters, the conne ..
74F569SJ ,4-Bit Bidirectional Counter with 3-STATE OutputsFeaturesThe 74F569 is a fully synchronous, reversible counter with Synchronous counting and loadin ..
74F573 ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional Description Function TableThe 74F573 contains eight D-type latches with 3-state out-Inpu ..
74F573. ,Octal D-Type Flip-Flop with 3-STATE Outputs54F/74F573OctalD-TypeLatchwithTRI-STATEOutputsAugust199554F/74F573OctalD-TypeLatchwithTRI-STATEÉOut ..
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7438SJ
Quad 2-Input NAND Buffers with Open-Collector Outputs
DM7438 • 7438 Quad 2-Input NAND Buffers with Open-Collector Outputs September 1986 Revised February 2000 DM7438 • 7438 Quad 2-Input NAND Buffers with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic NAND function. The open-collector out- puts require external pull-up resistors for proper logical operation. Where: N (I ) = total maximum output high current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input high current for 2 IH all inputs tied to pull-up resistor N (I ) = total maximum input low current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM7438M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM7438N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 7438SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LL H LH H HL H HH L H = HIGH Logic Level L = LOW Logic Level © 2000 DS006513
