7429 Fast Delivery |IC PHOENIX CO.,LIMITED

7429 ,VOLTAGE DETECTORapplications in TV and Hi-Fi systems, providing alsoFigure 1. Test Circuit2.2μF 2.2μF0.47μF 0.47μF ..
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7429
VOLTAGE DETECTOR
1/16
TDA7429L
March 20003 STEREO INPUTS AUXILIARY MONO INPUT INPUT ATTENUATION CONTROLIN 0.5dB
STEP TREBLE MIDDLE AND BASS CONTROL FOUR SPEAKERS ATTENUATORS:4 INDEPENDENT SPEAKERS CONTROLIN
1dB STEPS FOR BALANCE FACILITY INDEPENDENT MUTE FUNCTION SUBWOOFER OUTPUT (L+R) CONTROLLED 1dB STEP INPUTS ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7429Lis volume tone (bass middleandtre-
ble) balance (Left/Right) processorsfor quality audio
applicationsinTV and Hi-Fi systems, providing also additional subwoofer control.
TheAC signal settingis obtainedby resistor networks
and switches combinedwith operational amplifiers.
Thankstothe used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise andDC steppingareob-
tained.
SDIP42
ORDERING NUMBER: TDA7429L BAND EQUALIZER AUDIO PROCESSOR
WITH SUBWOOFER CONTROL
Figure1. Test Circuit
N.C.
N.C.
N.C.
N.C.
N.C.
LP1100nF
VAR_L
2.2μF
HP2
BASSO_LVAR_RBASSO_R
AUXOUT_L AUXOUT_R L_OUT R_OUT
CREF
100nF10μF
22μF
220nF
R_IN3
0.47μF
R_IN2
0.47μF
DIG_GNDSCLSDA AGND
18nF
2.7K
MIDDLE_LO
MIDDLE_LI
22nF
18nF
2.7K
MIDDLE_RO
MIDDLE_RI
22nF
100nF
5.6K
BASS_LO
BASS_LI
100nF
100nF
5.6K
BASS_RO
BASS_RI
100nF
TREBLE_L5.6nF
D99AU1029
2.2μF
TREBLE_R100nF
MONITOR_R
100nF 31 30 29 28 2726 25 12 11 39
MONOINPUT
0.47μF
L+R OUTPUT9 10 R_IN1
0.47μF
L_IN1
0.47μF
L_IN2 0.47μF
L_IN3 0.47μF
MONITOR_L36
TDA7429L
2/16
Figure2.Pin Connection
Table1. Quick Reference Data
Symbol Parameter Min. Typ. Max. Unit Supply Voltage 7 9 10.2 V
VCL Max. input signal handling 2 Vrms
THD Total Harmonic DistortionV= 1Vrmsf= 1KHz 0.01 0.1 %
S/N Signalto Noise RatioVout= 1Vrms (mode= OFF) 106 dB Channel Separationf= 1KHz 90 dB
Treble Control (2db step) -14 +14 dB
Middle Control (2db step) -14 +14 dB
Bass Control (2dB step) -14 +14 dB
Balance Control1dB step (LCH, RCH) -79 0 dB
Mute Attenuation 100 dB
AUXOUT_R
AUXOUT_L
L_IN3
L_IN1
L_IN2
MONITOR_L
MONITOR_R
R_IN1
R_IN2
D99AU1028
R_IN3
CREF
MIDDLE_RI
TREBLE_R
TREBLE_L
SCL
SDA
DIG_GND
R_OUT
LP1
N.C.
HP2
L+R OUTPUT
MONO INPUT
BASSO_L
VAR_L
VAR_R
BASSO_R
N.C.
N.C.
N.C.
N.C.
BASS_LO
BASS_LI
BASS_RO
MIDDLE_LO
BASS_RI
MIDDLE_LI
MIDDLE_RO
L_OUT
AGND
3/16
TDA7429L
Figure3. Block Diagram.
L_IN1
SUPPLY
AGND
CREF
TREBLE
18nF
MIDDLE
2.7K
MIDDLE_LI
MIDDLE_LO
22nF
BASS
BASS_LI
MUTE
D99AU1030
MUTE
I2C
BUS
DECODER
LATCHES
SPKR
ATT
REC ATT
TREBLE
MIDDLE
BASS
18nF
22nF
2.7K
5.6nF
MUTE
SPKR
ATT
MUTE
REC ATT
SCLSDADIG
GND
R_OUT AUXOUT_RL_OUTAUXOUT_L
LP1
HP2
100nF
R_IN3
50K
LPF
OFF
LPF
L+R
CONTROL
100nF
MIDDLE_RI
MIDDLE_RO 272628 29 31
MONITOR_R
TREBLE_R
79dB
CONTROL
5.6nF
TREBLE_L
100nF
5.6K
100nF
BASS_LO
100nF
100nF
5.6K
BASS_RI
BASS_RO
79dB
CONTROL
79dB
CONTROL
BASSO_R
VAR_R
30K
BASSO_L
VAR_L
30K
79dB
CONTROL
50K
50K
50K
50K
50K
31.5dB
control
R_IN2R_IN1
31.5dB
control
L_IN2 L_IN3
50K
REARIN
L+R
OUTPUT 33 38 39
Vref
OFF
OFF
SURRREAR
FIX
3BAND
SURR REAR
FIX
3BAND
FIX
VAR
FIX
VAR
THE
SWITCHES
POSITION
MATCHES
THE
RESET
CONDITION
MONITOR_L
TDA7429L
4/16
Table2. Thermal Data
Symbol Description Value Unit
Rthj-pins Thermal Resistance Junction-pins Max. 85 °C/W
Table3. Absolute Maximum Ratings
Symbol Parameter Value Unit Operating Supply Voltage 11 V
Tamb Operating Ambient Temperature -10to85 °C
Tstg Storage Temperature Range -55to +150 °C
Table4. Electrical Characteristics
(refertothe test circuitTamb =25°C,VS =9V,RL= 10KΩ,Vin =1Vrms;RG= 600Ω,all controlsflat= 0dB), L+R CTRL= +4dB, MODE= OFF;f= 1KHz unless otherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY Supply Voltage 7 9 10.2 V Supply Current 10 18 26 mA
SVR Ripple Rejection LCH /RCHout, Mode= OFF 60 80 dB
INPUT STAGE
RIN Input Resistance 35 50 65 KΩ
VCL Clipping Level THD= 0.3% 2 2.5 Vrms
CRANGE Control Range 31.5 dB
AVMIN Min. Attenuation -1 0 1 dB
AVMAX Max. Attenuation 31 31.5 32 dB
ASTEP Step Resolution 0.5 1 dB
BASS CONTROL Control Range Max. Boost/cut ±11.5 ±14.0 ±16.0 dB
BSTEP Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ
MIDDLE CONTROL Control Range Max. Boost/cut ±11.5 ±14.0 ±16.0 dB
MSTEP Step Resolution 1 2 3 dB Internal Feedback Resistance 17.5 25 32.5 KΩ
TREBLE CONTROL Control Range Max. Boost/cut ±13.0 ±14.0 ±15.0 dB
TSTEP Step Resolution 1 2 3 dB
5/16
TDA7429L
CONTROL L+R
CRANGE Control Range -11 +4 dB
SSTEP Step Resolution 0.5 1 1.5 dB
SPEAKER& AUX ATTENUATORS
CRANGE Control Range 79 dB
SSTEP Step Resolution -0.5 1 1.5 dB Attenuationset error Av=0to -20dB -1.5 0 1.5 dB=-20to -79dB -3 0 2 dB
VDC DC Steps adjacentatt. steps -3 0 3 mV
AMUTE Output Mute Condition +70 100 dB
RVEA Input Impedance 21 30 39 KΩ
AUDIO OUTPUTS
NO(OFF) Output Noise (OFF) Output Mute,Flat= 20Hzto 20KHz
μVrms
μVrms Distorsion Av=0;Vin =1Vrms 0.01 0.1 % Channel Separation 70 90 dB
VOCL Clipping Level d= 0.3% 2 2.5 Vrms
ROUT Output Resistance 20 40 70 Ω
VOUT DC Voltage Level 3.8 V
MONITOR OUTPUTS Distorsion Av=0;Vin =1Vrms 0.01 0.1 % Channel Separation 70 90 dB
VOCL Clipping Level d= 0.3% 2 2.5 Vrms
ROUT Output Resistance 20 50 70 Ω
VOUT DC Voltage Level 4.5 V
BUS INPUTS
VIL Input Low Voltage 1V
VIH Input High Voltage 3 V
IIN Input Current -5 +5 mA Output Voltage SDA
Acknowledge= 1.6mA 0.4 V
Table4. Electrical Characteristics
(refertothe test circuitTamb =25°C,VS =9V,RL= 10KΩ,Vin =1Vrms;RG= 600Ω,all controlsflat= 0dB), L+R CTRL= +4dB, MODE= OFF;f= 1KHz unless otherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
TDA7429L
6/16
1.0I2C BUS INTERFACE
Data transmission from microprocessortothe TDA7429L and viceversa takes place throughthe2 wiresI2C
BUS interface, consistingofthetwo lines SDA and SCL (pull-up resistorsto positive supply voltage mustbe
connected).
1.1 Data Validity showninfig.3,the dataonthe SDAline mustbe stable duringthe high periodofthe clock. The HIGH and
LOW stateofthe datalinecan only change whenthe clock signalonthe SCLlineis LOW.
1.2 Start and Stop Conditions shownin fig.4a start conditionisa HIGHto LOW transitionofthe SDAline while SCLis HIGH. The stop
conditionisa LOWto HIGH transitionofthe SDAline while SCLis HIGH.
1.3 Byte Format
Every byte transferredonthe SDAline must contain8 bits. Each byte mustbe followedbyan acknowledgebit.
The MSBis transferred first.
1.4 Acknowledge
The master (mP) putsa resistive HIGH levelonthe SDAline duringthe acknowledge clock pulse (seefig.5).
The peripheral (audioprocessor) that acknowledges hasto pull-down (LOW)the SDA line during this clock
pulse.
The audioprocessor whichhas been addressed hasto generatean acknowledge afterthe receptionof each
byte, otherwisethe SDAline remainsatthe HIGH level duringthe ninth clock pulse time.Inthis casethe master
transmittercan generatethe STOP informationin orderto abortthe transfer.
1.5 Transmission without Acknowledge
Avoidingto detectthe acknowledgeofthe audioprocessor,theμPcan usea simpler transmission: simplyit
waits one clock without checkingthe slave acknowledging, and sendsthe new data.
This approachof courseis less protected from misworking.
Figure4. Data validityontheI2 Cbus
Figure5. Timing DiagramofI2C bus
SDA
SCL
DATALINE
STABLE,DATA
VALID
CHANGE
DATA
ALLOWED D99AU1031
SCL
SDA
START2 CBUS
STOPD99AU1032
7/16
TDA7429L
Figure6. AcknowledgeontheI2C bus
2.0 SOFTWARE SPECIFICATION
2.1 Interface Protocol
The interface protocol comprises:A start condition(S)A chip address byte, containingthe TDA7429L addressA subaddress bytesA sequenceof data(N byte+ achnowledge)A stop condition(P)
3.0 EXAMPLES
3.1 No Incremental Bus
The TDA7429L receivesa start condition,the correct chip address,a subaddress withthe MSB=0(no incre-
mental bus), N-datas(all these datas concernthe subaddress selected),a stop condition.
3.2 Incremental Bus
The TDA7429L receivesa start condition,the correct chip address,a subaddress withthe MSB=1 (incremental
bus): nowitisina loop condition withan autoincreaseofthe subaddress whereas SUBADDRESS from
”1XXX1010”to ”1XXX1111”of DATAare ignored.The DATA1 concern thesubaddress sent, andthe DATA2
concernthe subaddress sent plusoneinthe loopetc,andattheendit receiversthe stop condition.
SCL 1
MSB
237 89
SDA
START ACKNOWLEDGMENT
FROMRECEIVERD99AU1033
ACK= Acknowledge S= Start P= Stop A= Address B= Auto Increment100000A0 ACK ACK DATA ACKP
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU226A DATA
SUBADDRESS DATA1to DATAn100000A0 ACK ACK DATA ACKP
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU306
0D3
SUBADDRESS DATAX D2D1D0100000A0 ACK ACK DATA ACKP
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU307
1D3
SUBADDRESS DATA1 toDATAnX D2D1D0
TDA7429L
8/16
Table5. Function Selection
Thefirst byte (subaddress)
MSB LSB
SUBADDRESS D6 D5 D4 D3 D2 D1 D01
<1> B=1 incrementalbus; active=0no incrementalbus;2
<2> X= indifferent0,1 X 0000 INPUT ATTENUATION X X X 0001 CONTROL OUT L+R&
SUBWOOFER X X X 0010 NOT USED X X X 0011 BASS& NATURAL BASE X X X 0100 MIDDLE& TREBLE X X X 0101 SPEAKER ATTENUATION”L“ X X X 0111 AUX ATTENUATION”L” X X X 1000 AUX ATTENUATION”R” X X X 1001 INPUT MULTIPLEXER,& AUX OUT
Table6. Input Attenuation Selection
MSB LSB INPUT ATTENUATION D6 D5 D4 D3 D2 D1 D0 0.5dB STEPS 000 0 0 0 1 -0.5 010 -1 0 1 1 -1.5 100 -2 1 0 1 -2.5 110 -3 1 1 1 -3.5dB STEPS 0 0 0 0 1 -4 1 0 -8 1 1 -12 0 0 -16 0 1 -20 1 0 -24 1 1 -28
INPUT ATTENUATION=0~ -31.5dB D6 D5 D4 D3 D2 D1 D0 L+R OUTPUT SWITCH 0 (L+R) OUTPUTPIN ACTIVE

Partno	Mfg	Dc	Qty	Available	Descript
7429	IR	N/a	7	avai	VOLTAGE DETECTOR