73S1215F-44M/F/PC ,80515 System-on-Chip with USB, ISO 7816/EMV, PINpad, and MoreFEATURES Communication Interfaces: 80515 Core: • Full-duplex serial interface (1200 to • 1 clock cy ..
73S8009C-32IM/F ,Versatile Power Management and Smart Card Interface IC
73S8009C-32IM/F ,Versatile Power Management and Smart Card Interface IC
73S8009R-IMR/F ,Low-Cost Versatile Smart Card Interface
73S8014R-ILR/F ,Smart Card Interface
73S8023C-IM/F ,Smart Card Interface
74F381PC ,4-Bit Arithmetic Logic UnitFeaturesThe 74F381 performs three arithmetic and three logic oper- Low input loading minimizes dri ..
74F381SJX , 4-Bit Arithmetic Logic UnitFeaturesThe 74F381 performs three arithmetic and three logic oper- Low input loading minimizes dri ..
74F381SJX , 4-Bit Arithmetic Logic Unit74F381 4-Bit Arithmetic Logic UnitMay 1988Revised August 199974F3814-Bit Arithmetic Logic Unit
74F382PC ,4-Bit Arithmetic Logic UnitFeaturesThe 74F382 performs three arithmetic and three logic oper-
73S1215F-44M/F/PC
80515 System-on-Chip with USB, ISO 7816/EMV, PINpad, and More
73S1215F
80515 System-on-Chip with USB,
ISO 7816 / EMV, PINpad and MoreSimplifying System Integration™
DATA SHEET
December 2008
GENERAL DESCRIPTION The 73S1215F is a versatile and economical
CMOS System-on-Chip device intended for smart
card reader applications. The circuit features an
ISO 7816 / EMV interface, an USB 2.0 interface
(full-speed 12Mbps device) and a 5x6 PINpad
interface. Maximum design flexibility is supported
with additional features such as 9 user I/Os,
multiple interrupt options, up to 4 programmable
current outputs (to drive external LEDs), and 1
analog voltage input (suitable for DC voltage
monitoring such as battery level detection). Other
built-in hardware interfaces include an
asynchronous serial UART and an I2C interface.
The System-on-Chip is built around an 80515 high
performance core. Its feature and instruction set is
compatible with the industry standard 8051, while
offering one clock-cycle per instruction processing
power (most instructions)With a CPU clock running
up to 24MHz, it results in up to 20 MIPS available
that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA
(for PIN encryption for instance). The circuit
requires a single crystal, which frequency can be
between 6MHz and 12MHz. In addition, a 32768
Hz sub-system oscillator (optional) with an
independent real-time-clock counter enables stand-
alone applications to access an RTC value. The
respective 73S1215F embedded memories are;
64KB Flash program memory, 2KB user XRAM
memory, and 256B IRAM memory. In addition to
these memories are independent FIFOs dedicated
to the ISO7816 UART and to the USB interface.
Overall, the 73S1215F offers a cost effective
solution to implement hand-held PINpad smart card
readers - USB connected, serial connected,
standalone or combo – as well as turnkey smart
card reader modules, USB or ExpressCard® type.
Embedded Flash memory is in-system
programmable and lockable by means of on-silicon
fuses. This makes the Teridian 73S1215F suitable
for both development and production phases.
Teridian Semiconductor Corporation offers with
its 73S1215F a very comprehensive set of
software libraries, including the smart card and
USB protocol layers that are pre-approved
against USB, Microsoft WHQL and EMV, as
well as a CCID reference design. Refer to the
73S12xxF Software User’s Guide for a
complete description of the Application
Programming Interface (API Libraries) and
related software modules.
A complete array of development and
programming tools, libraries and demonstration
boards enable rapid development and
certification of smart card readers that meet
most demanding smart card standards.
APPLICATIONS • Hand-held PINpad smart card readers: Connected through USB, serial or
un-connected
o CCID-compliant • E-banking (MasterCard CAP, etc) • Smart card reader modules for PC laptops
and desktops: ExpressCard® , USB • Digital Identification (Secure Login, Gov’t ID, ...) • General purpose smart card readers
ADVANTAGES • The ideal balance of cost and features for
high volume, USB-connected PINpad type
of applications: Larger built-in Flash / RAM than its
competitors Higher performance CPU core Powerful In-Circuit- Emulation and
Programming A complete set of ready-to-use EMV4.1 /
USB / CCID libraries
73S1215F Data Sheet DS_1215F_003
FEATURES
80515 Core: • 1 clock cycle per instruction (most instructions) • CPU clocked up to 24MHz • 64kB Flash memory with security • 2kB XRAM (User Data Memory) • 256 byte IRAM • Hardware watchdog timer
Oscillators: • Single low-cost 6MHz to 12MHz crystal • Optional 32768 Hz crystal (with internal RTC) • An Internal PLL provides all the necessary
clocks to each block of the system
Interrupts: • Standard 80C515 4-priority level structure • Nine different sources of interrupt to the core
Power Down Modes: • 2 standard 80C515 Power Down and IDLE
modes • Extensive device power down mode
Timers: • Two standard 80C52 timers T0 and T1 • One 16-bit timer that can generate RTC
interrupts from the 32kHz clock
Built-in ISO-7816 Card Interface: • LDO regulator produces VCC for the card
(1.8V, 3V or 5V) • Full compliance with EMV 4.1 • Activation/Deactivation sequencers • Auxiliary I/O lines (C4-C8 signals) • 6kV ESD protection on all interface pins
Communication with Smart Cards: • ISO 7816 UART for protocols T=0, T=1 • (2) 2-Byte FIFOs for transmit and receive • Configured to drive multiple external Teridian
73S8010x interfaces (for multi-SAM
architectures)
Communication Interfaces: • Full-duplex serial interface (1200 to
115kbps UART) • USB 2.0 Full Speed 12Mbps Interface,
PC/SC compliant with 4 Endpoints: • Control (16B FIFO) • Interrupt IN (32B FIFO) • Bulk IN (128B FIFO) • Bulk OUT (128B FIFO) • I2C Master Interface (400kbps)
Man-Machine Interface and I/Os: • 5x6 Keyboard (hardware scanning,
debouncing and scrambling) • Nine User I/Os • Up to 4 programmable current outputs
(LED)
Voltage Detection: • Analog Input (detection range: 1.0V to 1.5V)
Operating Voltage: • 2.7V to 3.6V (3V to 3.6V when USB is in use) • 4.75 to 5.5V for smart card supply
Operating Temperature: • -40°C to 85°C
Packages: • 68-pin QFN • 44-pin QFN
Software: • Two-level Application Programming Interface
(ANSI C-language libraries) • USB, T=0/T=1 and EMV-compliant smart card
protocol layers • CCID reference design and Windows® driver
DS_1215F_003 73S1215F Data Sheet
Table of Contents Hardware Description ......................................................................................................................... 8 1.1 Pin Description .............................................................................................................................. 8
1.2 Hardware Overview .................................................................................................................... 11
1.3 80515 MPU Core ........................................................................................................................ 11
1.3.1 80515 Overview ............................................................................................................. 11
1.3.2 Memory Organization .................................................................................................... 11
1.4 Program Security ........................................................................................................................ 16
1.5 Special Function Registers (SFRs) ............................................................................................ 18
1.5.1 Internal Data Special Function Registers (SFRs) .......................................................... 18
1.5.2 IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19
1.5.3 External Data Special Function Registers (SFRs) ........................................................ 20
1.6 Instruction Set ............................................................................................................................. 23
1.7 Peripheral Descriptions ............................................................................................................... 23
1.7.1 Oscillator and Clock Generation .................................................................................... 23
1.7.2 Power Control Modes .................................................................................................... 27
1.7.3 Interrupts ........................................................................................................................ 33
1.7.4 UART ............................................................................................................................. 40
1.7.5 Timers and Counters ..................................................................................................... 45
1.7.6 WD Timer (Software Watchdog Timer) ......................................................................... 47
1.7.7 User (USR) Ports ........................................................................................................... 50
1.7.8 Real-Time Clock with Hardware Watchdog (RTC) ........................................................ 52
1.7.9 Analog Voltage Comparator .......................................................................................... 55
1.7.10 LED Drivers ................................................................................................................... 57
1.7.11 I2C Master Interface ....................................................................................................... 58
1.7.12 Keypad Interface ............................................................................................................ 65
1.7.13 Emulator Port ................................................................................................................. 72
1.7.14 USB Interface ................................................................................................................ 72
1.7.15 Smart Card Interface Function ...................................................................................... 76
1.7.16 VDD Fault Detect Function .......................................................................................... 110
Typical Application Schematic ...................................................................................................... 111 Electrical Specification ................................................................................................................... 112 3.1 Absolute Maximum Ratings ...................................................................................................... 112
3.2 Recommended Operating Conditions ...................................................................................... 112
3.3 Digital IO Characteristics .......................................................................................................... 113
3.4 Oscillator Interface Requirements ............................................................................................ 114
3.5 DC Characteristics: Analog Input ............................................................................................. 114
3.6 USB Interface Requirements .................................................................................................... 115
3.7 Smart Card Interface Requirements ......................................................................................... 117
3.7.1 DC Characteristics ....................................................................................................... 119
3.8 Voltage / Temperature Fault Detection Circuits ....................................................................... 119
Equivalent Circuits ......................................................................................................................... 120 Package Pin Designation ............................................................................................................... 129 5.1 68-pin QFN Pinout .................................................................................................................... 129
5.2 44-pin QFN Pinout .................................................................................................................... 130
Packaging Information ................................................................................................................... 131 6.1 68-Pin QFN Package Outline ................................................................................................... 131
6.2 44-Pin QFN Package Outline ................................................................................................... 132
Ordering Information ...................................................................................................................... 133 Related Documentation .................................................................................................................. 133
73S1215F Data Sheet DS_1215F_003
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 7
Figure 2: Memory Map ................................................................................................................................ 15
Figure 3: Clock Generation and Control Circuits ........................................................................................ 24
Figure 4: Oscillator Circuit ........................................................................................................................... 26
Figure 5: Power Down Control .................................................................................................................... 27
Figure 6: Detail of Power Down Interrupt Logic .......................................................................................... 28
Figure 7: Power Down Sequencing ............................................................................................................ 28
Figure 8: External Interrupt Configuration ................................................................................................... 33
Figure 9: Real Time Clock Block Diagram .................................................................................................. 52
Figure 10: I2C Write Mode Operation .......................................................................................................... 59
Figure 11: I2C Read Operation .................................................................................................................... 60
Figure 12: Simplified Keypad Block Diagram .............................................................................................. 65
Figure 13: Keypad Interface Flow Chart .................................................................................................... 67
Figure 14: USB Block Diagram ................................................................................................................... 72
Figure 15: Smart Card Interface Block Diagram ......................................................................................... 76
Figure 16: Smart Card Interface Block Diagram ......................................................................................... 77
Figure 17: Asynchronous Activation Sequence Timing .............................................................................. 79
Figure 18: Deactivation Sequence .............................................................................................................. 80
Figure 19: Smart Card CLK and ETU Generation ...................................................................................... 81
Figure 20: Guard, Block, Wait and ATR Time Definitions ........................................................................... 82
Figure 21: Synchronous Activation ............................................................................................................. 84
Figure 22: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 84
Figure 23: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode ................................. 85
Figure 24: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 85
Figure 25: Operation of 9-bit Mode in Sync Mode ...................................................................................... 86
Figure 26: 73S1215F Typical Application Schematic ............................................................................... 111
Figure 27: 12 MHz Oscillator Circuit ......................................................................................................... 120
Figure 28: 32kHz Oscillator Circuit ........................................................................................................... 120
Figure 29: Digital I/O Circuit ...................................................................................................................... 121
Figure 30: Digital Output Circuit ................................................................................................................ 121
Figure 31: Digital I/O with Pull Up Circuit .................................................................................................. 122
Figure 32: Digital I/O with Pull-Down Circuit ............................................................................................. 122
Figure 33: Digital Input Circuit ................................................................................................................... 123
Figure 34: Keypad Row Circuit ................................................................................................................. 123
Figure 35: Keypad Column Circuit ............................................................................................................ 124
Figure 36: LED Circuit ............................................................................................................................... 125
Figure 37: Test and Security Pin Circuit ................................................................................................... 125
Figure 38: Analog Input Circuit .................................................................................................................. 126
Figure 39: Smart Card Output Circuit ....................................................................................................... 126
Figure 40: Smart Card I/O Circuit.............................................................................................................. 127
Figure 41: PRES Input Circuit ................................................................................................................... 127
Figure 42: PRES Input Circuit ................................................................................................................... 128
Figure 43: USB Circuit .............................................................................................................................. 128
Figure 44: 73S1215F 68 QFN Pinout ....................................................................................................... 129
Figure 45: 73S1215F 44 QFN Pinout ....................................................................................................... 130
Figure 46: 73S1215F 68 QFN Package Drawing ..................................................................................... 131
Figure 47: 73S1215F 44 QFN Package Drawing ..................................................................................... 132
DS_1215F_003 73S1215F Data Sheet
Tables
Table 1: 73S1215F Pinout Description ......................................................................................................... 8
Table 2: MPU Data Memory Map ................................................................................................................ 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................. 18
Table 7: IRAM Special Function Registers Reset Values ........................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register Flags ...................................................................................................................... 22
Table 10: PSW Bit Functions ...................................................................................................................... 22
Table 11: Port Registers ............................................................................................................................. 23
Table 12: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25
Table 13: The MCLKCtl Register ................................................................................................................ 25
Table 15: The MPUCKCtl Register ............................................................................................................. 26
Table 17: The INT5Ctl Register .................................................................................................................. 29
Table 19: The MISCtl0 Register .................................................................................................................. 29
Table 21: The MISCtl1 Register .................................................................................................................. 30
Table 23: The MCLKCtl Register ................................................................................................................ 31
Table 25: The PCON Register .................................................................................................................... 32
Table 27: The IEN0 Register ....................................................................................................................... 34
Table 29: The IEN1 Register ....................................................................................................................... 35
Table 31: The IEN2 Register ....................................................................................................................... 35
Table 33: The TCON Register .................................................................................................................... 36
Table 35: The T2CON Register .................................................................................................................. 36
Table 37: The IRCON Register ................................................................................................................... 37
Table 39: External MPU Interrupts .............................................................................................................. 37
Table 40: Control Bits for External Interrupts .............................................................................................. 38
Table 41: Priority Level Groups ................................................................................................................... 38
Table 42: The IP0 Register ......................................................................................................................... 38
Table 43: The IP1 Register ......................................................................................................................... 39
Table 44: Priority Levels .............................................................................................................................. 39
Table 45: Interrupt Polling Sequence .......................................................................................................... 39
Table 46: Interrupt Vectors .......................................................................................................................... 39
Table 47: UART Modes ............................................................................................................................... 40
Table 48: Baud Rate Generation ................................................................................................................ 40
Table 49: The PCON Register .................................................................................................................... 41
Table 51: The BRCON Register ................................................................................................................. 41
Table 53: The MISCtl0 Register .................................................................................................................. 42
Table 55: The S0CON Register .................................................................................................................. 43
Table 57: The S1CON Register .................................................................................................................. 44
Table 59: The TMOD Register .................................................................................................................... 45
Table 61: Timers/Counters Mode Description ............................................................................................ 46
Table 62: The TCON Register .................................................................................................................... 47
Table 64: The IEN0 Register ....................................................................................................................... 48
Table 66: The IEN1 Register ....................................................................................................................... 48
Table 68: The IP0 Register ......................................................................................................................... 49
Table 70: The WDTREL Register ............................................................................................................... 49
Table 72: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 50
Table 73: UDIR Control Bit .......................................................................................................................... 50
Table 74: Selectable Controls Using the UxIS Bits ..................................................................................... 50
Table 75: The USRIntCtl1 Register ............................................................................................................ 51
Table 76: The USRIntCtl2 Register ............................................................................................................ 51
Table 77: The USRIntCtl3 Register ............................................................................................................ 51
Table 78: The USRIntCtl4 Register ............................................................................................................ 51
