73M1903-IMR/F ,Modem Analog Front-EndElectrical Specifications .. 26 8.1 Absolute Maximum Ratings 26 8.2 Recommended Operating Conditio ..
73M2901CLIGT , V.22 BIS SINGLE CHIP MODEM
73M2901CLIH , V.22 BIS SINGLE CHIP MODEM
73S1215F-44M/F/PC ,80515 System-on-Chip with USB, ISO 7816/EMV, PINpad, and MoreFEATURES Communication Interfaces: 80515 Core: • Full-duplex serial interface (1200 to • 1 clock cy ..
73S8009C-32IM/F ,Versatile Power Management and Smart Card Interface IC
73S8009C-32IM/F ,Versatile Power Management and Smart Card Interface IC
74F378SJ ,Parallel D-Type Register with Enable54F/74F378ParallelDRegisterwithEnableJanuary199554F/74F378ParallelDRegisterwithEnableGeneralDescrip ..
74F378SJ ,Parallel D-Type Register with EnableFunctional Description Truth TableThe 74F378 consists of six edge-triggered D-type flip-flopsInputs ..
74F378SJ ,Parallel D-Type Register with Enable54F/74F378ParallelDRegisterwithEnableJanuary199554F/74F378ParallelDRegisterwithEnableGeneralDescrip ..
74F378SJX , Parallel D-Type Register with EnableFeaturesThe 74F378 is a 6-bit register with a buffered common 6-bit high-speed parallel registerEn ..
74F378SJX , Parallel D-Type Register with Enable74F378 Parallel D-Type Register with EnableApril 1988Revised August 199974F378Parallel D-Type Regis ..
74F378SJX , Parallel D-Type Register with EnableFunctional Description Truth TableThe 74F378 consists of six edge-triggered D-type flip-flopsInputs ..
73M1903-IM/F-73M1903-IMR/F
Modem Analog Front-End
73M1903
Modem Analog Front End
Simplifying System IntegrationTM DATA SHEET
March 2010
DESCRIPTION The Teridian 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs, which
connect to the telephone line interface through a
transformer-based DAA. The receive pins are also
fully differential for maximum flexibility and
performance. This arrangement allows for the
design of a high performance hybrid circuit to
improve signal to noise performance under low
receive level conditions, and compatibility with any
standard transformer intended for PSTN
communications applications.
The device incorporates a programmable sample
rate circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
14.4 kHz by programming pre-scaler NCO and PLL
NCO.
The 73M1903 device incorporates a digital host
interface that is compatible with the serial ports
found on most commercially available DSPs and
processors and exchanges both payload and control
information with the host.
Cost-saving features of the device include an input
reference frequency circuit, which accepts a range
of crystals from 9-27 MHz. It also accepts external
reference clock values between 9-40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of material
(BOM).
The 73M1903 also supports two analog loop back
and one digital loop back test modes.
Receive
Mux/
Filters
Transmit
Drivers/
Filters
TXAP
TXAN
(HYBRID)
DAA
Controls
RXAP
RXAN
HOOK
Analog
Sigma
Delta
Control
Registers
Ref.
ClocksControl
Logic
DAC
VBG
Serial
Port
SCLK
SDIN
SDOUT
FSB
GPIO
FEATURES • Up to 56 kbps (V.92) performance • Programmable sample rates (7.2 - 14.4 kHz) • Reference clock range of 9-40 MHz • Crystal frequency range of 9-27 MHz • Host synchronous serial interface operation • Pin compatible with 73M2901CL/CE
modems • Low power modes • On board line interface drivers • Fully differential receiver and transmitter • Drivers for transformer interface • 3.0 V – 3.6 V operation • 5 V tolerant I/O • Industrial temperature range (-40 to +85 °C) • JATE compliant transmit spectrum • Package options: • 32-pin QFN • 20-pin TSSOP • RoHS compliant (6/6) lead-free packages
APPLICATIONS • Set Top Boxes • Personal Video Recorders (PVR) • Multifunction Peripherals (MFP) • Fax Machines • Internet Appliances • Game Consoles • Point of Sale Terminals • Automatic Teller Machines • Speaker Phones • RF Modems
73M1903 Data Sheet DS_1903_032
Table of Contents Signal Description ......................................................................................................................... 4 1.1 Serial Interface ........................................................................................................................ 5
Control and Status Registers ........................................................................................................ 8 2.1 GPIO .................................................................................................................................... 10
2.1.1 GPIO Data (GPIO): Address 02h .............................................................................. 10
2.1.2 GPIO Direction (DIR): Address 03h .......................................................................... 10
2.2 Analog I/O ............................................................................................................................. 10
2.2.1 Control Register (CTRL 11): Address 0Bh ................................................................. 11
2.2.2 Control Register (CTRL 12): Address 0Ch ................................................................. 11
2.2.3 Control Register (CTRL 13): Address 0Dh ................................................................. 12
2.2.4 Control Register (CTRL 14): Address 0Eh ................................................................. 12
Clock Generation ......................................................................................................................... 13 3.1 Crystal Oscillator and Pre-scaler NCO................................................................................... 13
3.1.1 Control Register (CTRL 8): Address 08h .................................................................... 13
3.1.2 Control Register (CTRL 9): Address 09h .................................................................... 13
3.1.3 Control Register (CTRL 10): Address 0Ah ................................................................. 13
Modem Receiver .......................................................................................................................... 18 Modem Transmitter ..................................................................................................................... 21 5.1 Transmit Levels..................................................................................................................... 22
5.2 Transmit Power - dBm........................................................................................................... 23
5.3 Control Register (CTRL1): Address 00h ............................................................................... 23
5.4 Control Register (CTRL2): Address 01h ............................................................................... 24
5.5 Revision Register: Address 06h ............................................................................................ 24
Test Modes................................................................................................................................... 25 Power Saving Modes ................................................................................................................... 25 Electrical Specifications .............................................................................................................. 26 8.1 Absolute Maximum Ratings ................................................................................................... 26
8.2 Recommended Operating Conditions .................................................................................... 26
8.3 Digital Specifications ............................................................................................................. 27
8.3.1 DC Characteristics..................................................................................................... 27
8.3.2 AC Timing ................................................................................................................. 28
8.4 Analog Specifications ............................................................................................................ 29
8.4.1 DC Specifications ...................................................................................................... 29
8.4.2 AC Specifications ...................................................................................................... 29
8.5 Performance ......................................................................................................................... 30
8.5.1 Receiver .................................................................................................................... 30
8.5.2 Transmitter ................................................................................................................ 31
Pinouts ......................................................................................................................................... 33 9.1 32-Pin QFN Pinout ................................................................................................................ 33
9.2 20-Pin TSSOP Pinout ........................................................................................................... 34
10 Mechanical Specifications .......................................................................................................... 35 10.1 32-Pin QFN Mechanical Drawings ......................................................................................... 37
10.2 20-Pin TSSOP Mechanical Drawings .................................................................................... 38
11 Ordering Information ................................................................................................................... 39
Appendix A – 73M1903 DAA Resistor Calculation Guide .................................................................. 40
Appendix B – Crystal Oscillator .......................................................................................................... 42
Revision History .................................................................................................................................. 47 DS_1903_032 73M1903 Data Sheet
Figures Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0 ....................................................... 7
Figure 2: Control Frame Position versus SPOS ........................................................................................ 7
Figure 3: Serial Port Timing Diagram ....................................................................................................... 9
Figure 4: Analog Block Diagram ............................................................................................................. 11
Figure 5: Clock Generation .................................................................................................................... 17
Figure 6: Overall Receiver Frequency Response ................................................................................... 19
Figure 7: Rx Passband Response .......................................................................................................... 19
Figure 8: RXD Spectrum of 1 kHz Tone ................................................................................................. 20
Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes ......... 20
Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal ........................................... 21
Figure 11: Serial Port Data Timing ......................................................................................................... 28
Figure 12: 32-Pin QFN Pinout ................................................................................................................ 33
Figure 13: 20-Pin TSSOP Pin out .......................................................................................................... 34
Figure 14: 73M1903 Schematic ............................................................................................................. 35
Figure 14: 32-Pin QFN Mechanical Specifications .................................................................................. 37
Figure 15: 20-Pin TSSOP Mechanical Specifications ............................................................................. 38
Figure 16: NCO Block Diagram .............................................................................................................. 42
Figure 17: PLL Block Diagram ............................................................................................................... 43
Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 4
Table 2: Memory Map .............................................................................................................................. 8
Table 3: PLL Loop Filter Settings ........................................................................................................... 11
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C .................................................................................. 13
Table 5: PLL Power Down ..................................................................................................................... 14
Table 6: Examples of NCO Settings ....................................................................................................... 14
Table 7: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................ 15
Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz ...................................................... 16
Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz ........................................................ 16
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz .................................................... 17
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz ...................................................... 17
Table 12: Receive Gain ......................................................................................................................... 18
Table 13: Peak to RMS Ratios for Various Modulation Types ................................................................. 23
Table 14: Serial I/F Timing ..................................................................................................................... 28
Table 15: Reference Voltage Specifications ........................................................................................... 29
Table 16: Maximum Transmit Levels ...................................................................................................... 29
Table 17: Receiver Performance Specifications ..................................................................................... 30
Table 18: Transmitter Performance Specifications ................................................................................. 31
Table 19: 32-Pin QFN Pin Definitions ..................................................................................................... 33
Table 20: 20-Pin TSSOP Pin Definitions ................................................................................................ 34
Table 21: Bill of Materials ....................................................................................................................... 36
Table 22: Ordering Information .............................................................................................................. 39
73M1903 Data Sheet DS_1903_032
Signal Description The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the
same pin out. The following table describes the function of each pin. There are two pairs of power
supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately
isolate and decouple these supplies will compromise device performance.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Pin Name Type 32QFN
Pin #
20VT
Pin# Description VND GND 1,22 2,18 Negative Digital Ground
VNA GND 16 13 Negative Analog Ground
VPD PWR 2,25 3 Positive Digital Supply
VPA PWR 10 8 Positive Analog Supply
VPPLL PWR 20 17 Positive PLL Supply, shared with VPD
VNPLL PWR 17 14 Negative PLL Ground
RST I 9 7 Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high- default.
OSCIN I 19 16 Crystal oscillator input. When providing an external clock
source, drive OSCIN.
OSCOUT O 18 15 Crystal oscillator circuit output pin.
GPIO(0-7) I/O
3, 4, 5, 6,
23,
24,30,31
N/A
Software definable digital input/output pins. Not available in
the 20VT (TSSOP) package.
VREF O 13 6 Reference voltage pin (Reflects VREF).
RXAP I 15 12 Receive analog positive input.
RXAN I 14 11 Receive analog negative input.
TXAP O 12 10 Transmit analog positive output.
TXAN O 11 9 Transmit analog negative output.
SCLK O 8 5 Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
SDOUT O 32 1 Serial data output (or input to the host).
SDIN I 29 20 Serial data input (or output from the host).
FS O 7 4 Frame synchronization. (Active Low)
TYPE I 27 19 Type of frame sync. Open, weak-pulled high = early
(mode1); tied low = late (mode0).
SckMode I 28 NA
Controls the SCLK behavior after FS. Open, weak-pulled
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not available in 20VT.
DS_1903_032 73M1903 Data Sheet
1.1 Serial Interface The serial data port is a bi-directional port that is supported by many DSPs. Although the 73M1903 is a
peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial
bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that is
programmed by the user. The serial bit clock is derived by dividing the system clock by 18. The sclk rate,
Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk /
256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which
both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document
two pairs of sample rates, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions.
They are:
1. Fxtal1 = 27 MHz, Fs1 = 7.2 kHz
2. Fxtal2 = 18.432 MHz, Fs2 = 8 kHz.
3. Fxtal3 = 24.576 MHz, Fs3 = 9.6 kHz – chip default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be Sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz.
2. If Fxtal2 = 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz.
3. If Fxtal3 = 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz.
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs1 = 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
2. If Fs2 = 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz.
3. If Fs3 = 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition is forced on or after the second Frame
Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data FS is generated by the 73M1903 at the rate of Fs. For every data FS
there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin
programmable for type. FS can either be early or late determined by the state of the TYPE input pin.
When the TYPE pin is left open, an early FS is generated in the bit clock prior to the first data bit
transmitted or received. When held low, a late FS operates as a chip select; the FS signal is active for all
bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active (low)
and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines
the frame synchronization mode used.
73M1903 Data Sheet DS_1903_032
The bits transmitted on the SDOUT pin are defined as follows:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN
are defined as follows:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
In this case TX0=0 is forced.
If the Hardware Control bit (bit 0 of register 01h) is set to one, the 16 bits that are received on the SDIN
input are defined as follows:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit
code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data
frames. If the hardware control bit is set to zero, CTL (TX bit 0) is used by software to request a control
frame. If CTL is high, a control frame is initiated before the next data frame. A control frame allows the
controller to read or write status and control to the 73M1903.
The control word received on the SDIN pin is defined as follows:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
The control word transmitted on the SDOUT pin is defined as follows:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
If the R/W bit is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received
on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is
set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data
contained in the register pointed to by address bits A6-A0. Only one control frame can occur between
any two data frames.
Writes to unimplemented registers are ignored. Reading an unimplemented register returns a value of 0.
The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is set to a 0
the control frames occur mid way between data frames, i.e., the time between data frames is equal. If
SPOS is set to a 1, the control frame is ¼ of the way between consecutive data frames, i.e., the control
frame is closer to the first data frame. This is illustrated in Figure 2.
New to the 73M1903 modem AFE IC is a feature that shuts off the serial clock (SCLK) after 32 cycles of
SCLK following the frame synch (Figure 1). This feature is unavailable in the 20 TSSOP package
option. This mode is controlled by the SckMode pin. If this pin is left open, the clock will run continuously. If SckMode is low the clock will be gated on for 32 clocks for each FS. The SDOUT and FS
pins change values following a rising edge of SCLK. The SDIN pin is sampled on the falling edge of
DS_1903_032 73M1903 Data Sheet
SCLK and FS in mode 1
SCLK
FS(mode1)
32 Cycles of sclk
SCLK and FS in mode 0
FS(mode0)
SCLK
32 Cycles of sclk
Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0
Figure 2: Control Frame Position versus SPOS 73M1903 Data Sheet DS_1903_032
Control and Status Registers Table 2 shows the memory map of addressable registers in the 73M1903. Each register and its bits are
described in detail in the following sections.
Table 2: Memory Map
Address Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 08h ENFE Unused TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN
01 00h TMEN DIGLB ANALB INTLB Reserved RXPULL SPOS HC
02 FFh GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
03 FFh DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
04 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
05 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
06 10h Rev3 Rev2 Rev1 Rev0 Unused Reserved Reserved Reserved
07 00h Unused
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
08 00h Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
09 0Ah Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
0A 22h Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
0B 12h Unused Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
0C 00h Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
0D C0h Xtal1 Xtal0 Reserved Reserved Unused Nrst2 Nrst1 Nrst0
0E 00h Frcvco PwdnPLL Reserved Unused Unused Unused Unused Unused
0F-7F Unused Unused Unused Unused Unused Unused Unused Unused
To prevent unintended operation, do not write to reserved or unused locations. These locations are for
factory test or future use only and are not intended for customer programming.
DS_1903_032 73M1903 Data Sheet
FS(mode1)
TX15TX12TX11TX10TX9TX13TX8TX7TX6TX5TX4TX3TX2TX1CTLTX14
RX15RX12RX11RX10RX9RX13RX8RX7RX6RX5RX4RX3RX2RX1RX0RX14
Data Frame With Early Frame Sync
SCLK
SDIN
SDOUT
R/WA4A3A2A1A5A0DI7DI6DI5DI4DI3DI2DI1DI0A6
zerozerozerozerozerozerozeroDO7DO6DO5DO4DO3DO2DO1DO0zero
Control Frame With Early Frame Sync
SCLK
SDIN
SDOUT
FS(mode1)
R/WA4A3A2A1A5A0DI7DI6DI5DI4DI3DI2DI1DI0A6
zerozerozerozerozerozerozeroDO7DO6DO5DO4DO3DO2DO1DO0zero
Control Frame With Late Frame Sync
SCLK
SDIN
SDOUT
FS(mode0)
SCLK
SDIN
SDOUTTXTXTXTX1RXRXRXRXRXAADIDIDI00DODODOTXTXTXTX0RXRXRXRXRX
7.2KHz (8KHz)
Data FrameControl FrameData Frame
Relation Between the Data and Control Frames
Figure 3: Serial Port Timing Diagram
73M1903 Data Sheet DS_1903_032
2.1 GPIO The 73M1903 modem AFE device provides 8 user defined I/O pins. Each pin is programmed separately
as either an input or an output by a bit in a direction register. If the bit in the direction register is set high,
the corresponding pin is an input whose value is read from the GPIO data register. If it is low, the pin will
be treated as an output whose value is set by the GPIO data register.
To avoid unwanted current contention and consumption in the system from the GPIO port before the
GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input
structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins.
The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO
direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.
2.1.1 GPIO Data (GPIO): Address 02h
Reset State FFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Bits in this register will be asserted on the GPIO(7:0) pins if the corresponding direction register bit is a 0.
Reading this address will return data reflecting the values of pins GPIO(7:0).
2.1.2 GPIO Direction (DIR): Address 03h
Reset State FFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
This register is used to designate the GPIO pins as either inputs or outputs. If the register bit is low, the
corresponding GPIO pin is programmed as an output. If the register bit is a 1, the corresponding pin will
be treated as an input.
2.2 Analog I/O Figure 4 shows the block diagram of the analog front end. The analog interface circuit uses differential
transmit and receive signals to and from the external circuitry.
The hybrid driver in the 73M1903 IC is capable of connecting directly, but not limited to, a transformer-
based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s line coupling
transformer, which carries an impedance on the primary side that is typically rated at 600 Ω, depending
on the transformer and matching network. The hybrid drivers can also drive high impedance loads
without modification. The class AB behavior of the amplifiers provides load dependent power
consumption.
An on-chip band gap voltage is used to provide an internal voltage reference and bias currents for the
analog receive and transmit channels. The reference derived from the bandgap, nominally 1.25 Volts, is
multiplied to 1.36 Volts and output at the VREF pin. Several voltage references, nominally 1.25 Volts, are
used in the analog circuits. The band gap and reference circuits are disabled after a chip reset since the
ENFE bit is reset to a default state of zero. When ENFE=0, the band gap voltage and the analog bias
currents are disabled. In this case all of the analog circuits are powered down and draw less than 5 μA of
current.
A clock generator (CKGN) is used to create all of the non-overlapping phase clocks needed for the time
sampled switched-capacitor circuits, ASDM, DAC1, and TLPF. The CKGN input is two times the
analog/digital interface sample rate or 3.072 MHz clock for Fs=8 kHz.
DS_1903_032 73M1903 Data Sheet
Figure 4: Analog Block Diagram
Table 3: PLL Loop Filter Settings
FL PLLloop Filter Settings R1=32 kΩ,C1=100 pF,C2=2.5 pF R1=16 kΩ, C1=100 pF,C2=2.5 pF
2.2.1 Control Register (CTRL 11): Address 0Bh
Reset State 12h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored.
2.2.2 Control Register (CTRL 12): Address 0Ch
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
73M1903 Data Sheet DS_1903_032
2.2.3 Control Register (CTRL 13): Address 0Dh
Reset State 48h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Xtal1 Xtal0 Reserved Reserved Unused Nrst2 Nrst1 Nrst0
Xtal[1:0] : 00 = Xtal osc. bias current at 120 μA 01 = Xtal osc. bias current at 180 μA 10 = Xtal osc. bias current at 270 μA 11 = Xtal osc. bias current at 450 μA
If OSCIN is used as a Clock input, “00” setting should be used to save power(=167 μA at 27.648 MHz).
Nrst[3:0] represents the rate at which the NCO sequence register is reset.
The address 0Dh must be the last register to be written to when effecting a change in PLL.
2.2.4 Control Register (CTRL 14): Address 0Eh
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frcvco PwdnPLL Reserved Unused Unused Unused Unused Unused
Frcvco = 1 forces VCO as system clock. This is reset upon RST, PwdnPLL = 1 or ENFE = 0. Both
PwdnPLL and ENFE are delayed coming out of digital section to keep PLL alive long enough to transition
the system clock to crystal clock when Frcvco is reset by PwdnPLL or ENFE.
PwdnPll = 1 forces Power down of PLL analog section.
DS_1903_032 73M1903 Data Sheet
Clock Generation
3.1 Crystal Oscillator and Pre-scaler NCO The crystal oscillator operates over wide choice of crystals (from 9 MHz to 27 MHz) and it is first input to
an NCO based pre-scaler (divider) prior to being passed onto an on-chip PLL
Appendix B
. The intent of the pre-
scaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a
reference frequency, Fref, for the PLL. The NCO pre-scaler requires a set of three numbers to be
entered through the serial port (Pseq[7:0], Prst[2:0] and Pdvsr[2:0]. The PLL also requires 3 numbers as
for programming; Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers
that control the NCOs, PLLs, and sample rates for the 73M1903 IC. The tables show some examples of
the register settings for different clock and sample rates. A more detailed discussion on how these values
are derived can be found in .
3.1.1 Control Register (CTRL 8): Address 08h
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
This corresponds to the sequence of divisor. If Prst{2:0] =0 this register is ignored.
3.1.2 Control Register (CTRL 9): Address 09h
Reset State 0Ah
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
Prst[2:0] represents the rate at which the sequence register is reset.
Pdvsr[4:0] represents the divisor.
3.1.3 Control Register (CTRL 10): Address 0Ah
Reset State 22h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
Kvco2:0 represents the magnitude of Kvco associated with the VCO within PLL. This indicates the center
frequency of the VCO when the control voltage is 1.6 Volts and the slope of the VCO freq versus control
voltage (i.e., Kvco.). FL represents the PLL loop filter settings.
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C
Kvco2 Kvco1 Kvco0 Fvco Kvco 0 0 33 MHz 38 MHz/v 0 1 36 MHz 38 MHz/v 1 0 44 MHz 40 MHz/v 1 1 48 MHz 40 MHz/v 0 0 57 MHz 63 MHz/v 0 1 61 MHz 63 MHz/v 1 0 69 MHz 69 MHz/v 1 1 73 MHz 69 MHz/v
73M1903 Data Sheet DS_1903_032
Table 5: PLL Power Down
Addr. 00h bit 7
ENFE
Addr. 0Eh bit 6
PwdnPLL PLL X PLL Power Off 0 PLL Power On 1 PLL Power Off
Table 6: Examples of NCO Settings Fs
(kHz)
Dnco1
Nnco1 PsSeq(7:0) PsRst
=Dnco1
-1
Dnco2
Nnco2
llDPllSeq(7:0) PllRst
=Dnco2
-1
Fvco
(Mhz)
PPM 7.2 8/125 15 11011010 7 5/96 19 XXX10000 4 33.177600 0
8.0 8/125 15 11011010 7 3/64 21 XXXXX100 2 36.864000 0
2.4*8/7*3
=8.22857142858
8/169
21 10000000 7
3/89
29 XXXXX110 2 37.917160* -3
8.4 8/125 15 11011010 7 5/112 22 XXX10100 4 38.707200 0
9.0 8/125 15 11011010 7 1/24 24 XXXXXXXX 0 41.472000 0
9.6 8/125 15 11011010 7 5/128 25 XXX11010 4 44.236800 0
2.4*10/7*3
=10.2857142857
8/125
15 11011010 7
7/192
27 X1010110 6 47.396571 0
2.4*8/7*4
=10.9714285714
7/50 X1000000 6
8/107
13 10100100 7 50.557500* 23
11.2* 7/52 7 X1010100 6 5/71 14 XXX10000 4 51.611538* 38
12.0 8/125 15 11011010 7 1/32 32 XXXXXXXX 0 55.296000 0
12.8* 8/65 8 10000000 7 4/71 17 XXXX1110 3 58.984615* 38
2.4*10/7*4
=13.7142857143
7/80
11 X1010100 6
4/107
26 XXXX1110 3 63.196875* 23
14.4 8/125 15 11011010 7 5/192 38 XXX10100 4 66.355200 0
7.2 1/10 10 XXXXXXXX 0 2/27 13 XXXXXX10 1 33.177600 0
8.0 1/10 10 XXXXXXXX 0 1/15 15 XXXXXXXX 0 36.864000 0
2.4*8/7*3
=8.22857142858
4/35 XXXX1110 3 2/27 13 XXXXXX10 1 37.917257… 0
8.4 1/10 10 XXXXXXXX 0 4/63 15 XXXX1110 3 38.707200 0
9.0 1/10 10 XXXXXXXX 0 8/135 16 11111110 7 41.472000 0
9.6 1/10 10 XXXXXXXX 0 1/18 18 XXXXXXXX 0 44.236800 0
2.4*10/7*3
=10.2857142857
3/28 9 XXXXX100 2 1/18 18 XXXXXXXX 0 47.3965714.. 0
2.4*8/7*4
=10.9714285714
4/35 8 XXXX1110 3
1/18 18 XXXXXXXX 0 50.5563429.. 0
11.2 1/10 10 XXXXXXXX 0 1/21 21 XXXXXXXX 0 51.609600 0
12 1/10 10 XXXXXXXX 0 2/45 22 XXXXXX10 1 55.296000 0
12.8 1/10 10 XXXXXXXX 0 1/24 24 XXXXXXXX 0 58.982400 0
2.4*10/7*4
=13.7142857143
1/7 7 XXXXXXXX 0
1/18 18 XXXXXXXX 0 63.19542… 0
14.4 1/10 10 XXXXXXXX 0 1/27 27 XXXXXXXX 0 66.355200 0
7.2 1/4 4 XXXXXXXX 0 5/72 14 XXX10100 4 33.177600 0
8.0 1/4 4 XXXXXXXX 0 1/16 16 XXXXXXXX 0 36.864000 0
8.4 1/4 4 XXXXXXXX 0 5/84 16 XXX11110 4 38.707200 0
9.0 1/4 4 XXXXXXXX 0 1/18 18 XXXXXXXX 0 41.472000 0
9.6 1/4 4 XXXXXXXX 0 5/96 19 XXX10000 4 44.236800 0
2.4*8/7*4
=10.9714285714
2/7 XXXXXX10 4
5/96
19 XXX10000 4 50.556343 0
DS_1903_032 73M1903 Data Sheet
Fs
(kHz)
Dnco1
Nnco1 PsSeq(7:0) PsRst
=Dnco1
-1
Dnco2
Nnco2
llDPllSeq(7:0) PllRst
=Dnco2
-1
Fvco
(Mhz)
PPM 12.8 1/4 4 XXXXXXXX 0 5/128 25 XXX11010 4 58.982400 0
14.4 1/8 8 XXXXXXXX 0 5/288 57 XXX11010 4 66.355200 0
7.2 8/125 15 11011010 7 5/108 21 XXX11010 4 33.1776 0
8.0 2/25 12 XXXXXX10 1 5/96 19 XXX10000 4 36.864 0
2.4*8/7*3
=8.22857142858 4/73 18 XXXX1000 3 6/173 28 XX111110 5 37.91781* 15
8.4 8/125 15 11011010 7 5/126 25 XXX10000 4 38.7072 0
9.0 4/25 6 XXXX1000 3 5/54 10 XXX11110 4 41.472 0
9.6 8/125 15 11011010 7 5/144 28 XXX11110 4 44.2368 0
2.4*10/7*3
=10.2857142857 8/125 15 11011010 7 7/216 30 X1111110 6 47.39657 0
2.4*8/7*4
=10.9714285714 6/59 9 XX111110 5 7/145 20 X1110110 6 50.5569* 12
11.2 8/125 15 11011010 7 5/168 33 XXX11010 4 51.6096 0
12.0 4/25 6 XXXX1000 3 5/72 14 XXX10100 4 55.296 0
12.8 8/125 15 11011010 7 5/192 38 XXX10100 4 58.9824 0
2.4*10/7*4
=13.7142857143 5/61 12 XXX10000 4 8/257 32 10000000 7 63.19672* 21
14.4 7/73 10 X1010100 6 6/173 28 XX111110 5 66.35616* 15
25.7.2 8/163 20 10010010 7 3/80 26 110 2 33.177914* 10
Table 7: Clock Generation Register Settings for Fxtal = 27 MHz
Reg Address
Fs (kHz) 8h 9h Ah Bh Ch
Ichp
(μA)
Kvco
[2:0] 7.2 DA EF 20 13 10 C4 8 0
8.0 DA EF 31 15 04 C2 10 1
2.4*8/7*3
=8.22857142858 80 F5 41 1D 06 C2 12 1
8.4 DA EF 31 16 14 C4 10 1
9.0 DA EF 31 18 XX C0 10 1
9.6 DA EF 32 19 1A C4 10 2
2.4*10/7*3
=10.2857142857 DA EF 43 1B 54 C6 12 3
2.4*8/7*4
=10.9714285714* 40 C7 23 0D A4 C7 8 3
11.2* 54 C7 23 0E 10 C4 8 3
12.0 DA EF 24 20 XX C0 8 4
12.8* 80 E8 15 11 0E C3 6 5
2.4*10/7*4
=13.7142857143 54 CB 26 1A 0E C3 8 6
14.4 DA EF 46 26 14 C4 12 6
73M1903 Data Sheet DS_1903_032
Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz
Reg Address
Fs (kHz) 8h 9h Ah Bh Ch Dh*
Ichp (μA)
Kvco
[2:0] 7.2 XX 0A 10 0D 02 C1 6 0
8.0 XX 0A 11 0F XX C0 6 1
2.4*8/7*3
=8.22857142858 0E 68 11 0D 02 C1 6 1
8.4 XX 0A 21 0F 0E C3 8 1
9.0 XX 0A 21 10 FE C7 8 1
9.6 XX 0A 22 12 XX C0 8 2
2.4*10/7*3
=10.2857142857 04 49 23 12 XX C0 8 3
2.4*8/7*4
=10.9714285714 0E 68 23 12 XX C0 8 3
11.2 XX 0A 23 15 XX C0 8 3
12 XX 0A 14 16 02 C1 6 4
12.8 XX 0A 15 18 XX C0 6 5
2.4*10/7*4
=13.7142857143 XX 07 16 12 XX C0 6 6
14.4 XX 0A 26 1B XX C0 8 6
Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz
Reg
Address
Fs (kHz) 8h 9h Ah Bh Ch Dh*
Ichp
(μA)
Kvco
[2:0] 7.2 XX 04 20 0E 14 C4 8 0
8.0 XX 04 31 10 XX C0 10 1
8.4 XX 04 31 10 1E C4 10 1
9.0 XX 04 31 12 XX C0 10 1
9.6 XX 04 32 13 10 C4 10 2
2.4*8/7*4
=10.9714285714 02 23 33 13 10 C4 10 3
11.2 XX 04 33 16 14 C4 10 3
12 XX 04 24 18 XX C0 8 4
12.8 XX 04 35 19 1A C4 10 5
14.4 XX 08 66 39 1A C4 16 6
DS_1903_032 73M1903 Data Sheet
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz
Reg Address
Fs (kHz) 8h 9h Ah Bh Ch Dh*
Ichp (μA)
Kvco
[2:0] 7.2 DA EF 30 15 1A C4 10 0
8.0 02 2C 31 13 10 C4 10 1
2.4*8/7*3
=8.22857142858 08 72 41 1C 3E C5 12 1
8.4 DA EF 41 19 10 C4 12 1
9.0 08 66 11 0A 1E C4 6 1
9.6 DA EF 42 1C 1E C4 12 2
2.4*10/7*3
=10.2857142857 DA EF 43 1E 7E C6 12 3
2.4*8/7*4
=10.9714285714 3E A9 33 14 76 C6 10 3
11.2 DA EF 53 21 1A C4 14 3
12 08 66 14 0E 14 C4 6 4
12.8 DA EF 45 26 14 C4 12 5
2.4*10/7*4
=13.7142857143 10 8C 46 20 80 C7 12 6
14.4 54 CA 46 1C 3E C5 12 6
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz
Reg Address
FS (KHz) 8h 9h Ah Bh Ch Dh*
Ichp
(μA)
Kvco
[2:0] 7.2 92 F4 50 1A 06 C2 14 0
Xtal Oscillator
System
Clock
NCOIchp Control
VCO Locked
Fref
FvcoKvco Control
Fxtal
NCO
Prescaler
VCO
KvcoPFDCharge
PumpFrcVco
Loop Filter Control
73M1903 Data Sheet DS_1903_032
Modem Receiver A differential receive signal applied at the RXAP and RXAN pins or the output signal at TXAP and TXAN
pass through a multiplexer, which selects the inputs to the ADC. In normal mode, RXAP/RXAN are
selected. In analog loopback mode, TXAP/TXAN are selected. The DC bias for the RXAP/RXAN inputs
is supplied from TXAP/TXAN through the external DAA in normal conditions. (See Appendix A) It can be
supplied internally, in the absence of the external DAA, by setting RXPULL bit in Control Register 2.
The output of the multiplexer goes into a second-order continuous time, Sallen-Key, low-pass filter (AAF)
with a 3 dB point at approximately 40 kHz. The filtered output signal is the input to an analog sigma-delta
modulator (ASDM), clocked at an over sampling frequency of 1.536 MHz for Fs = 8 kHz, which converts
the analog signal to a serial bit stream with a pulse density that is proportional to the amplitude of the
analog input signal.
There are three gain control bits for the receive path. The RXGAIN bit in control register one results in a
+20 dB gain of the receive signal when set to a “1”. This 20 dB of gain compensates for the loss through
the DAA while on hook. It is used for Caller ID reception. This gain is realized in the front end of ASDM.
The other gain bits in control register 1, RXG1:0, compensate for differences in loss through the receive
path.
Table 12: Receive Gain
RXG1 RXG0 Receive Gain Setting 0 6 dB 1 9 dB 0 12 dB 1 0 dB
The output of ASDM is a serial bit stream that feeds three digital sinc3 filters. Each filter has a [sin(x)/x]3
frequency response and provides a 16 bit sample every 288 clock cycles. The filters are synchronized so
that there is one sample available after every 96 analog samples or at a rate of 16 kHz for Fs=8 kHz. The
output of the sinc3 filter is a 17 bit, two’s compliment number representing the amplitude of the input
signal. The sinc3 filter, by virtue of holding action (for 96 sample period), introduces a droop in the
passband that is later corrected for by a 48 tap FIR filter that follows. The maximum digital word that can
be output from the filter is 0d800h. The minimum word is 12800h.
The output of the sinc3 filter is input to another 48 tap digital FIR filter that provides an amplitude
correction in the passband to the output of the sinc3 filter as well as rejecting noise above Fs/2 or 4 kHz
for Fs=8 kHz. The output of this filter is then decimated by a factor of 2; so, the final output is 16 bit, two’s
compliment samples at a rate of 8 kHz.
Figure 6 and Figure 7 depict the sinc3 filter’s frequency response of ASDM along with the 48 tap digital
FIR response that compensates for it and the resulting overall response of the receiver.
DS_1903_032 73M1903 Data Sheet Figure 6: Overall Receiver Frequency Response Figure 7: Rx Passband Response
It is important to keep in mind that the receive signal should not exceed 1.16 Vpk-diff for proper
performance for Rxg=11 (0 dB). In particular, if the input level exceeds a value such that one’s density of
RBS exceeds 99.5%, sinc3 filter output will exceed the maximum input range of the decimation filter and
consequently the data will be corrupted. Also for stability reasons, the receive signal should not exceed
1.16 Vpk differentially. This value is set at around 65% of the full receive signal of 1.791 Vpkdiff at
RXAP/RXAN pins that “would” corresponds to ASDM putting out all ones.
Figure 8 and Figure 9 show the spectrum of 1 kHz tone received at RXAP/RXAN of 1.16 Vpk-diff and
0.5 kHz and 1.0 kHz tones of 0.6 Vpk-diff each, respectively for Fs=8 kHz. Note the effect of FIR
73M1903 Data Sheet DS_1903_032 Figure 8: RXD Spectrum of 1 kHz Tone
Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes
DS_1903_032 73M1903 Data Sheet Modem Transmitter
The modem transmitter begins with an 48 tap Transmit Interpolation Filter (TIF) that takes in the 16-bit,
two’s compliment numbers (TXD) at SDIN pin at Fs=8 kHz rate. It up-samples (interpolates) the data to
16 kHz rate rejecting the images at multiples of 8 kHz that exist in the original TXD data stream and
outputs 16-bit, two’s compliment numbers to a digital sigma-delta modulator. The gain of the interpolation
filter is 0.640625 (–3.8679 dB) at DC.
The digital sigma-delta modulator (DSDM) takes 16-bit, two’s compliment numbers as input and
generates a 1’s bit stream which feeds into a D to A converter (DAC1). The gain through DSDM is 1.0.
DSDM takes 16-bit, two’s compliment numbers as input and generates a 1’s bit stream that feeds into a D
to A converter (DAC1).
DAC1 consists of a 5-tap FIR filter and a first order switched capacitor low pass filter both operating at
1.536 MHz. It possesses nulls at multiples of 384 kHz to allow decimation by the succeeding filter.
DAC1’s differential output is fed to a 3rd-order switched-capacitor low pass filter (TLPF). The output of
TLPF drives a continuous time smoothing filter. The sampling nature of the transmitter leads to an
additional filter response that affects the in-band signals. The response is in the form of sin(x)/x and can
be expressed as 20*log [(sin(PI*f/fs))/(PI*f/fs)] where f = signal frequency and fs = sample frequency = 16
kHz. Figure 10 shows the frequency response of the transmit path from TXD to TXAP/TXAN for a dc to 4
kHz in-band signal including the effect of this sampling process plus those of DAC1, TLPF and SMFLT. It
is important to note that as TXD is sampled at 8 kHz, it be band-limited to 4 kHz.
Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal
73M1903 Data Sheet DS_1903_032
5.1 Transmit Levels
The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF)
has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will
result in a 0.5 (-6 dB) gain change in the analog output signal.
The following formula describes the relationship between the transmit code word and the output level at
the transmit pins (TXAP/TXAN):
Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr
Vout is the differential peak voltage at the TXAP and TXAN pins.
Code is the 16-bit, two’s compliment transmit code word written out by the DSP to the DSDM (via TIF).
The code word falls within a range of ± 32,767. For a sinusoidal waveform, the peak code word should
be used in the formula to obtain the peak output voltage.
DSDMgain is the scaling factor used on the transmit code word to reduce the possibility of saturating the
modulator. This value is set to 0.640625(–3.555821 dB) at dc in the 48 tap transmit interpolation filter
(TIF) that precedes DSDM.
dacGAIN is the gain of the DAC. The value dacGAIN is calculated based on capacitor values inside
DAC1 and dacGAIN=8/9=0.8889. The number 32,767 refers to the code word that generates an 82%
“1’s” pulse density at the output of the DSDM. As one can see from the formula, the D to A conversion is
dependent on the level of VREF. Also when TXBST1 bit is set, VREF is increased from 1.36 V to 1.586 V
to allow higher transmit level or 16.6% increase in gain. This bit is intended for enhancing the DTMF
transmit level and should not be used in data mode.
TLPFgain is the gain of TLPF and nominally equals to 0.00 dB or 1.0.
SMFLTgain is the gain of SMFLT and nominally equal to 1.445 or 3.2 dB.
When TXBST0 bit is set, the gain is further increased by 1.65 dB (1.21) for the total of 4.85 dB. This is to
accommodate greater hybrid insertion loss encountered in some applications.
FreqFctr shows dependency of the entire transmit path on frequency. See Figure 10.
With the transmit code word of +/- 32,767, the nominal differential swing at the transmit pins at dc is:
Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr
= 2 * 32,767/32767 * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.0 = 2.31Vpk diff.
When TXBST1 bit is set, Vout (V) = 1.166 * 2.31= 2.693 Vpk diff.
When TXBST0 bit is set, Vout (V) = 1.21 * 2.31= 2.795 Vpk diff, if not limited by power supply or internal
reference.
When both TXBST1 and TXBST0 are set to 1, Vout (V) = 1.166 * 1.21 * 2.31 = 3.259 Vpk diff.
DS_1903_032 73M1903 Data Sheet
5.2 Transmit Power - dBm
To calculate the analog output power, the peak voltage is calculated and the peak to rms ratio (crest
factor) must be known. The following formula is used to calculate the output power, in dBm referenced to
600 Ω.
Pout (dBm) = 10 * log [ ( Vout (V) / cf )2 / ( 0.001 * 600 ) ]
The following example demonstrates the calculation of the analog output power given a 1.2 kHz FSK tone
(sine wave) with a peak code word value of 11,878 sent out by the DSP.
The differential output voltage at TXAP-TXAN will be:
With FreqFctr = 1.02, (See Figure 10)
Vout (V) = 2 * (11,878/32,767) * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.02 = 0.841 Vpk.
The output signal power will be:
Pout (dBm) = 10 * log [(0.841 / 1.41)2 / (0.001 * 600) ] = - 2.29 dBm.
Table 13: Peak to RMS Ratios for Various Modulation Types
Transmit Type Crest Factor Max Line Level
V.90 4.0 -12 dBm
QAM 2.31 -9 dBm
DPSK 1.81 -9 dBm
FSK 1.41 -9 dBm
DTMF 1.99 -5.7 dBm
5.3 Control Register (CTRL1): Address 00h
Reset State 08h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ENFE Unused TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN
ENFE 1 = Enable the digital filters and analog front end. 0 = Disable the analog blocks shut off the clocks to the digital and analog receive/transmit
circuits.
TXBST1 1 = Add a gain of 1.335 dB (16.6%) to the transmitter; also the common mode voltage of the
transmit path is increased to 1.375 V. This is intended for enhancing DTMF transmit
power only and should not be used in data mode. 0 = No gain is added
TXBST0 1 = A gain of 1.65 dB (21%) is added to the transmitter 0 = The gain of the transmitter is nominal
TXDIS 1 = Tri-state the TXAP and TXAN pins, provides a bias of VBG into 80 kΩ for each output pin
RXG1:0 These bits control the receive gain as shown in Table 12.
RXGAIN 1 = Increase the gain of the receiver by 20 dB.
73M1903 Data Sheet DS_1903_032
5.4 Control Register (CTRL2): Address 01h
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TMEN DIGLB ANALB INTLB CkoutEn RXPULL SPOS HC
TMEN 1 = Enable test modes.
DIGLB 1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter
input. DIGITAL LOOPBACK
ANALB 1 = Tie the analog output of the transmitter to the analog input of the receiver. ANALOG
LOOPBACK
INTLB 1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter
input. INTERNAL LOOPBACK
CkoutEn 1 = Enable the CLKOUT output; 0 = CLKOUT tri-stated. For test purposes only; do not use
in normal operation.
RXPULL 1 = Pulls DC Bias to RXAP/RXAN pins, through 100 kΩ each, to VREF, to be used in testing
Rx path. 0 = No DC Bias to RXAP/RXAN pins.
SPOS 1 = Control frames occur after one quarter of the time between data frames has elapsed. 0 = Control frames occur half way between data frames.
HC 1 = FS is under hardware control, bit 0 of data frames on SDIN is bit 0 of the transmit word
and control frames happen automatically after every data frame. 0 = FS is under software control, bit 0 of data frames on SDIN is a control frame request bit
and control frames happen only on request.
5.5 Revision Register: Address 06h
Reset State 30h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Rev3 Rev2 Rev1 Rev0 Unused Reserved Reserved Reserved
Bits 7-4 contain the revision level of the 73M1903 device. The rest of this register is for chip development
purposes only and is not intended for customer use. Do not write to shaded locations.
