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5962L9583401VFA
LVDS Quad CMOS Differential Line Receiver
DS90C032
LVDS Quad CMOS Differential Line Receiver
General DescriptionTheDS90C032isa quad CMOS differential line receiver
designedfor applications requiring ultra low power dissipa-
tion and high data rates. The deviceis designedto support
data ratesin excessof 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032 accepts low voltage (350 mV) differential
input signals and translates themto CMOS (TTLcompatible)
output levels. The receiver supportsa TRI-STATE® function
that maybe usedto multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100Ω) input Fail-
safe with the additionof external failsafe biasing. Receiver
output willbe HIGHfor both Failsafe conditions.
TheDS90C032 and companion line driver (DS90C031) pro-
videa new alternativeto high power psuedo-ECLdevicesfor
high speed point-to-point interface applications.
Features >155.5 Mbps (77.7 MHz) switching rates Accepts small swing (350 mV) differential signal levels Ultra low power dissipation 600ps maximum differential skew (5V, 25˚C) 6.0ns maximum propagation delay Industrial operating temperature range Military operating temperature range option Availablein surface mount packaging (SOIC) and (LCC) Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL) Supports OPEN, short and terminated input fail-safe Compatible with IEEE 1596.3 SCI LVDS standard Conformsto ANSI/TIA/EIA-644 LVDS standard Availableto Standard Microcircuit Drawing (SMD)
Connection Diagrams
Dual-In-Line
Order Number
DS90C032TM
See NS Package Number M16A
LCC Package
Order Number
DS90C032E-QML
See NS Package Number E20A
For complete Military Specifications,
referto appropriate SMDor MDS.
September 2003
DS90C032
VDS
Quad
CMOS
Differential
Line
Receiver
