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5962-9469601VFA
Low-Skew Quad Clock Driver
Low-Skew Quad Clock Driver
General DescriptionThe 100315 contains fourlow skew differential drivers,de-
signedfor generationof multiple, minimum skew differential
clocks froma single differential input. This device alsohas
the capabilityto selecta secondary single-ended clock
sourceforusein lower frequency system level testing.The
100315isa300 Series redesignofthe 100115 clock driver.
Features Low outputto output skew (≤50ps) Differential inputsand outputs Secondary clock availablefor system level testing 2000V ESD protection Voltage compensated operating range: −4.2Vto −5.7V Standard Microcircuit Drawing
(SMD) 5962-9469601
Logic Diagram
Connection Diagram Pin Names DescriptionCLKIN, CLKIN Differential Clock Inputs
CLK1–4, CLK1–4 Differential Clock Outputs
TCLK Test Clock Input (Note1)
CLKSEL Clock Input Select (Note1)
Note1: TCLKandCLKSEL aresingle-ended inputs,withinternal 50kΩpull-
down resistors.
Truth Table
CLKSEL CLKIN CLKIN TCLK CLKN CLKN H X L H L X H L X L L H X H H L=Low Voltage Level=High Voltage Level= Don’tCare
DS100319-1
FlatpakDS100319-2
August 1998
Low-Skew
Quad
Clock
Driver 1998 National Semiconductor Corporation DS100319
