5962-9152101MXA ,4-channel Simultaneous Sampling, 12-Bit Data Acquisition SystemSPECIFICATIONSMIN MAXParameter A Version B Version S Version Units Test Conditions/CommentsSAMPLE-A ..
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5962-9152802MYA ,Low Power Quint 2-Input OR/NOR GateGeneral DescriptionThe 100302 is a monolithic quint 2-input OR/NOR gate with common Enable. All in ..
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744766220 , SMD-RF-Choke WE-GF
744766220 , SMD-RF-Choke WE-GF
744770015 , POWER-CHOKE WE-PD
74477007 , POWER-CHOKE WE-PD
744770112 , POWER-CHOKE WE-PD
74477110 , POWER-CHOKE WE-PD
5962-9152101MXA
4-channel Simultaneous Sampling, 12-Bit Data Acquisition System
REV.C
LC2MOS 4-Channel, 12-Bit Simultaneous
Sampling Data Acquisition System
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD7874 is a four-channel simultaneous sampling, 12-bit
data acquisition system. The part contains a high speed 12-bit
ADC, on-chip reference, on-chip clock and four track/hold am-
plifiers. This latter feature allows the four input channels to be
sampled simultaneously, thus preserving the relative phase
information of the four input channels, which is not possible if
all four channels share a single track/hold amplifier. This makes
the AD7874 ideal for applications such as phased-array sonar
and ac motor controllers where the relative phase information is
important.
The aperture delay of the four track/hold amplifiers is small and
specified with minimum and maximum limits. This allows sev-
eral AD7874s to sample multiple input channels simultaneously
without incurring phase errors between signals connected to
several devices. A reference output/reference input facility also
allows several AD7874s to be driven from the same reference
source.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7874 is also fully
specified for dynamic performance parameters including distor-
tion and signal-to-noise ratio.
The AD7874 is fabricated in Analog Devices’ Linear Compat-
ible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low-power CMOS
logic. The part is available in a 28-pin, 0.6" wide, plastic or her-
metic dual-in-line package (DIP), in a 28-terminal leadless ce-
ramic chip carrier (LCCC) and in a 28-pin SOIC.
FEATURES
Four On-Chip Track/Hold Amplifiers
Simultaneous Sampling of 4 Channels
Fast 12-Bit ADC with 8 ms Conversion Time/Channel
29 kHz Sample Rate for All Four Channels
On-Chip Reference610 V Input Range
65 V Supplies
APPLICATIONS
Sonar
Motor Controllers
Adaptive Filters
Digital Signal Processing
PRODUCT HIGHLIGHTS1. Simultaneous Sampling of Four Input Channels.
2. Tight Aperture Delay Matching.
3. Fast Microprocessor Interface.
AD7874–SPECIFICATIONS
(VDD = +5 V, VSS = –5 V, AGND = DGND = 0 V, REF IN = +3 V, fCLK = 2.5 MHz
external. All specifications TMIN to TMAX unless otherwise noted.)REFERENCE INPUT
NOTESTemperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.See Terminology.Sample tested @ +25°C to ensure compliance.
TIMING CHARACTERISTICS1NOTESTiming Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = O V, tCLK = 2.5 MHz external unless
otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . .0 V to VDD
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . .1,000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 1.Load Circuit for Access Time
Figure 2.Load Circuit for Bus Relinquish Time
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7874
TERMINOLOGY
ACQUISITION TIMEAcquisition Time is the time required for the output of the
track/hold amplifiers to reach their final values, within ±1/2
LSB, after the falling edge of INT (the point at which the track/
holds return to track mode). This includes switch delay time,
slewing time and settling time for a full-scale voltage change.
APERTURE DELAYAperture Delay is defined as the time required by the internal
switches to disconnect the hold capacitors from the inputs. This
produces an effective delay in sample timing. It is measured by
applying a step input and adjusting the CONVST input position
until the output code follows the step input change.
APERTURE DELAY MATCHINGAperture Delay Matching is the maximum deviation in aperture
delays across the four on-chip track/hold amplifiers.
APERTURE JITTERAperture Jitter is the uncertainty in aperture delay caused by
internal noise and variation of switching thresholds with signal
level.
DROOP RATEDroop Rate is the change in the held analog voltage resulting
from leakage currents.
CHANNEL-TO-CHANNEL ISOLATIONChannel-to-Channel Isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 1 kHz signal to the other three inputs. The figure given is
the worst case across all four channels.
SNR, THD, IMDSee DYNAMIC SPECIFICATIONS section.
PIN CONFIGURATIONS
DIP and SOIC
PIN FUNCTION DESCRIPTION9VDD
ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to part number. Contact
AD7874
CONVERTER DETAILSThe AD7874 is a complete 12-bit, 4-channel data acquisition
system. It is comprised of a 12-bit successive approximation
ADC, four high speed track/hold circuits, a four-channel analog
multiplexer and a 3 V Zener reference. The ADC uses a succes-
sive approximation technique and is based on a fast-settling,
voltage switching DAC, a high speed comparator, a fast CMOS
SAR and high speed logic.
Conversion is initiated on the rising edge of CONVST. All four
input track/holds go from track to hold on this edge. Conversion
is first performed on the Channel 1 input voltage, then Channel
2 is converted and so on. The four results are stored in on-chip
registers. When all four conversions have been completed, INT
goes low indicating that data can be read from these locations.
The conversion sequence takes either 78 or 79 rising clock edges
depending on the synchronization of CONVST with CLK. In-
ternal delays and reset times bring the total conversion time
from CONVST going high to INT going low to 32.5 μs maxi-
mum for a 2.5 MHz external clock. The AD7874 uses an im-
plicit addressing scheme whereby four successive reads to the
same memory location access the four data words sequentially.
The first read accesses Channel 1 data, the second read accesses
Channel 2 data and so on. Individual data registers cannot be
accessed independently.
INTERNAL REFERENCEThe AD7874 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 3 V ± 10 mV (see
Figure 3). The reference voltage is provided at the REF OUT
pin. This reference can be used to provide both the reference
voltage for the ADC and the bipolar bias circuitry. This is
achieved by connecting REF OUT to REF IN.
Figure 3.AD7874 Internal Reference
The reference can also be used as a reference for other compo-
nents and is capable of providing up to 500 μA to an external
load. In systems using several AD7874s, using the REF OUT of
one device to provide the REF IN for the other devices ensures
good full-scale tracking between all the AD7874s. Because the
AD7874 REF IN is buffered, each AD7874 presents a high im-
pedance to the reference so one AD7874 REF OUT can drive
several AD7874 REF INs.
The maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for other
system uses, it should be decoupled to AGND with a 200 Ω re-
EXTERNAL REFERENCEIn some applications, the user may require a system reference or
some other external reference to drive the AD7874 reference in-
put. Figure 4 shows how the AD586 5 V reference can be used
to provide the 3 V reference required by the AD7874 REF IN.
Figure 4.AD586 Driving AD7874 REF IN
TRACK-AND-HOLD AMPLIFIERThe track-and-hold amplifier on each analog input of the
AD7874 allows the ADC to accurately convert an input sine
wave of 20 V p-p amplitude to 12-bit accuracy. The input band-
width of the track/hold amplifier is greater than the Nyquist rate
of the ADC even when the ADC is operated at its maximum
throughput rate. The small signal 3 dB cutoff frequency occurs
typically at 500 kHz.
The four track/hold amplifiers sample their respective input
channels simultaneously. The aperture delay of the track/hold
circuits is small and, more importantly, is well matched across
the four track/holds on one device and also well matched from
device to device. This allows the relative phase information be-
tween different input channels to be accurately preserved. It also
allows multiple AD7874s to sample more than four channels
simultaneously.
The operation of the track/hold amplifiers is essentially transpar-
ent to the user. Once conversion is initiated, the four channels
are automatically converted and there is no need to select which
channel is to be digitized.
ANALOG INPUTThe analog input of Channel 1 of the AD7874 is as shown in
Figure 4. The analog input range is ±10 V into an input resis-
tance of typically 30 kΩ. The designed code transitions occur
midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSBs, 5/2 LSBs, . . . FS – 3/2 LSBs). The output code is
2s complement binary with 1 LSB = FS/4096 = 20 V/4096 =
4.88 mV. The ideal input/output transfer function is shown in
Figure 5.
Figure 5.Input/Output Transfer Function
OFFSET AND FULL-SCALE ADJUSTMENTIn most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error will have to be
adjusted to zero.
Figure 6 shows a circuit which can be used to adjust the offset
and full-scale errors on the AD7874 (Channel 1 is shown for ex-
ample purposes only). Where adjustment is required, offset er-
ror must be adjusted before full-scale error. This is achieved by
trimming the offset of the op amp driving the analog input of
the AD7874 while the input voltage is a 1/2 LSB below analog
ground. The trim procedure is as follows: apply a voltage of
–2.44 mV (–1/2 LSB) at V1 in Figure 6 and adjust the op amp
offset voltage until the ADC output code flickers between 1111
1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC posi-
tive full scale). The trim procedures for both cases are as
follows:
Positive Full-Scale AdjustApply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V1. Adjust
R2 until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale AdjustApply a voltage of –9.9976 V ( –FS + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
which use an external reference is to adjust the voltage at the
REF IN pin until the full-scale error for any of the channels is
adjusted out. The good full-scale matching of the channels will
ensure small full-scale errors on the other channels.
TIMING AND CONTROLConversion is initiated on the AD7874 by asserting the
CONVST input. This CONVST input is an asynchronous input
which is independent of the ADC clock. This is essential for
applications where precise sampling in time is important. In
these applications, the signal sampling must occur at exactly
equal intervals to minimize errors due to sampling uncertainty
or jitter. In these cases, the CONVST input is driven from a
timer or precise clock source. Once conversion is started,
CONVST should not be asserted again until conversion is com-
plete on all four channels.
In applications where precise time interval sampling is not criti-
cal, the CONVST pulse can be generated from a microproces-
sor WRITE or READ line gated with a decoded address
(different to the AD7874 CS address). CONVST should not be
derived from a decoded address alone because very short
CONVST pulses (which may occur in some microprocessor sys-
tems as the address bus is changing at the start of an instruction
cycle) could initiate a conversion.
All four track/hold amplifiers go from track to hold on the rising
edge of the CONVST pulse. The four track/hold amplifiers re-
main in their hold mode while all four channels are converted.
The rising edge of CONVST also initiates a conversion on the
Channel 1 input voltage (VIN1). When conversion is complete
on Channel 1, its result is stored in Data Register 1, one of four
on-chip registers used to store the conversion results. When the
result from the first conversion is stored, conversion is initiated
on the voltage held by track/hold 2. When conversion has been
completed on the voltage held by track/hold 4 and its result is
stored in Data Register 4, INT goes low to indicate that the
conversion process is complete.
The sequence in which the channel conversions takes place is
automatically taken care of by the AD7874. This means that the
user does not have to provide address lines to the AD7874 or
worry about selecting which channel is to be digitized.
Reading data from the device consists of four read operations to
the same microprocessor address. Addressing of the four
AD7874The first read operation to the AD7874 after conversion always
accesses data from Data Register 1 (i.e., the conversion result
from the VIN1 input). INT is reset high on the falling edge of
RD during this first read operation. The second read always ac-
cesses data from Data Register 2 and so on. The address pointer
is reset to point to Data Register 1 on the rising edge of
CONVST. A read operation to the AD7874 should not be at-
tempted during conversion. The timing diagram for the
AD7874 conversion sequence is shown in Figure 7.
DATA
INT
CONVST
HIGH-IMPEDANCE
TRACK/HOLDS GO
INTO HOLDHIGH-Z
TIMES t2, t3, t4, t6, t7, AND t8 ARE THE SAME FOR ALL FOUR READ OPERATIONS. Figure 7.AD7874 Timing Diagram
AD7874 DYNAMIC SPECIFICATIONSThe AD7874 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as Integral and Differential Nonlinearity. These ac specifications
are required for the signal processing applications such as
phased array sonar, adaptive filters and spectrum analysis.
These applications require information on the ADC’s effect on
the spectral content of the input signal. Hence, the parameters
for which the AD7874 is specified include SNR, harmonic dis-
tortion, intermodulation distortion and peak harmonics. These
terms are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)SNR is the measured signal to noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fs/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by
SNR = (6.02N + 1.76) dB(1)
where N is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input which is
sampled at a 29 kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be ob-
tained. Figure 8 shows a typical 2048 point FFT plot of the
AD7874BN with an input signal of 10 kHz and a sampling
frequency of 29 kHz. The SNR obtained from this graph is
Figure 8.AD7874 FFT Plot
Effective Number of BitsThe formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N). =SNR−1.76
6.02(2)
The effective number of bits for a device can be calculated di-
rectly from its measured SNR.
Figure 9 shows a typical plot of effective number of bits versus
frequency for an AD7874BN with a sampling frequency of
29 kHz. The effective number of bits typically falls between
11.75 and 11.87 corresponding to SNR figures of 72.5 dB and
73.2 dB.
Figure 9.Effective Numbers of Bits vs. Frequency
