5962-8995001SEA ,Dual JK Negative Edge Triggered Flip-FlopPin DescriptionsPin Names DescriptionPin Assigment forJ ,J ,K ,K Data InputsDIP and Flatpack 1 2 1 ..
5962-9052502MQA ,CMOS universal asynchronous receiver transmitter (UART), 8MHz = 500K BAUDFeatures Description• 8.0MHz Operating Frequency (HD-6402B) The HD-6402 is a CMOS UART for interfac ..
5962-9052604MXA ,Digital Signal ProcessorSMJ320C30DIGITALSIGNALPROCESSORSGUS014H -- FEBRUARY 1991 -- REVISED JUNE 20042D --55°Cto125°COperat ..
5962-9052701MXA , TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
5962-9063201MLA ,Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A)Specifications subject to change without notice.–2– REV. BAD7870/AD7875/AD7876 AD7875/AD78761 1 1 ..
5962-9065101MCA ,Quad 3-State BufferMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
744212100 , WE-SL1 SMD Common Mode Line Filter
744226 , COMMON MODE SMD LINE FILTER WE-SL2
744231371 , SMD common mode noise suppressor WE-CNSW
744232090 , SMD common mode noise suppressor WE-CNSW
744272471 , COMMON MODE SMD LINE FILTER WE-SL5
744311068 , WE-HCI SMD Flat Wire High Current Inductor
5962-8995001SEA
Dual JK Negative Edge Triggered Flip-Flop
54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General DescriptionThe ’ACT112 contains two independent, high-speedJK
flip-flops withDirect Setand Clear inputs.Synchronous state
changesareinitiatedby thefallingedgeof theclock. Trigger-
ing occursata voltage levelofthe clockandisnot directly
relatedtothe transition time.The Jand Kinputscan change
when theclockisin eitherstate without affectingthe flip-flop,
providedthat theyareinthe desired state duringthe recom-
mended setupand hold times relativetothe falling edgeof
the clock.A LOW signalonSDorCD prevents clockingand
forcesQorQ HIGH, respectively. Simultaneous LOWsig-
nalsonSDandCD force bothQandQ HIGH.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQandQ
HIGH
Features ’ACT112has TTL-compatible inputs Outputs source/sink24mA Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram Pin Descriptions
Pin Names DescriptionJ1,J2,K1,K2 Data Inputs
CP1,CP2 Clock Pulse Inputs
(Active Falling Edge)
CD1,CD2 Direct Clear Inputs (Active LOW)
SD1,SD2 DirectSet Inputs (Active LOW)
Q1,Q2,Q1,Q2 Outputs
FACT™isatrademark ofFairchildSemiconductor Corporation.
Pin Assigmentfor
DIP and FlatpackDS100976-3
Pin Assigment
for LCCDS100976-5
September 1998
54ACT1
Dual
Negative
Edge-T
riggered
Flip-Flop 1998 National Semiconductor Corporation DS100976
