CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC112 and ’HCT112 utilize ..
CD54HCT112F3A ,High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge TriggerCD54HC112, CD74HC112,CD54HCT112, CD74HCT112Data sheet acquired from Harris SemiconductorDual J-K Fl ..
CD54HCT11F. ,High Speed CMOS Logic Triple 3-Input AND GatesFeatures Description• Buffered Inputs The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOStec ..
CD54HCT11F3A ,High Speed CMOS Logic Triple 3-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT11F3A. ,High Speed CMOS Logic Triple 3-Input AND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CHPZ27VPT , SILICON PLANAR POWER ZENER DIODES
CHPZ6V2PT , SILICON PLANAR POWER ZENER DIODES
CHS-01TA , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-01TA1 , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-02TB , SURFACE MOUNT TYPE SLIDE SWITCHES
CHS-04MB , SURFACE MOUNT TYPE SLIDE SWITCHES
5962-8984301CA-CD54HCT10F3A
High Speed CMOS Logic Triple 3-Input NAND Gates
CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C High-Speed CMOS Logic Triple 3-Input NAND Gate August 1997 - Revised September 2003 Features Description [ /Title • Buffered Inputs The ’HC10 and ’HCT10 logic gates utilize silicon gate CMOS (CD74 technology to achieve operating speeds similar to LSTTL HC10, = 5V, • Typical Propagation Delay: 8ns at V CC gates with the low power consumption of standard CMOS o C = 15pF, T = 25 C CD74 L A integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin HCT10 • Fanout (Over Temperature Range) compatible with the standard LS logic family. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads ) - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Sub- / Ordering Information o o ject • Wide Operating Temperature Range . . . -55 C to 125 C TEMP. RANGE (High • Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE Speed • Significant Power Reduction Compared to LSTTL CD54HC10F3A -55 to 125 14 Ld CERDIP CMOS Logic ICs Logic CD54HCT10F3A -55 to 125 14 Ld CERDIP • HC Types Triple - 2V to 6V Operation CD74HC10E -55 to 125 14 Ld PDIP 3-Input - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC10M -55 to 125 14 Ld SOIC NAND at V = 5V CC Gate) CD74HC10MT -55 to 125 14 Ld SOIC • HCT Types /Autho - 4.5V to 5.5V Operation CD74HC10M96 -55 to 125 14 Ld SOIC r () - Direct LSTTL Input Logic Compatibility, CD74HCT10E -55 to 125 14 Ld PDIP /Key- V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT10M -55 to 125 14 Ld SOIC words l OL OH (High CD74HCT10MT -55 to 125 14 Ld SOIC Speed CD74HCT10M96 -55 to 125 14 Ld SOIC CMOS NOTE: When ordering, use the entire part number. The suffix 96 Logic denotes tape and reel. The suffix T denotes a small-quantity reel Triple of 250. 3-Input NAND Pinout Gate, CD54HC10, CD54HCT10 High (CERDIP) Speed CD74HC10, CD74HCT10 (PDIP, SOIC) CMOS TOP VIEW Logic Triple 1A 1 14 V CC 3-Input 1B 2 13 1C NAND 2A 3 12 1Y Gate, 2B 4 11 3C Harris 2C 5 10 3B Semi- 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
