5962-8859301MPA ,Dual Low Offset, Low Power Operational Amplifierapplications requiring multipleOP07, yet the OP200 offers significant improvements over thisprecisi ..
5962-8863401XX ,256 (32K x 8) high speed parallel EEPROM, 120nsfeatures to ensure highThe AT28HC256 is accessed like a Static RAM for the read quality and manufac ..
5962-8863401YX ,256 (32K x 8) high speed parallel EEPROM, 120nsfeatures protectasserted on the outputs. The outputs are put in the highagainst inadvertent writes ..
5962-8863402XX ,256 (32K x 8) high speed parallel EEPROM, 120nsfeatures to ensure highThe AT28HC256 is accessed like a Static RAM for the read quality and manufac ..
5962-8863402YX ,256 (32K x 8) high speed parallel EEPROM, 120nsFeatures• Fast Read Access Time - 70 ns• Automatic Page Write Operation– Internal Address and Data ..
5962-8863403XX ,256 (32K x 8) high speed parallel EEPROM, 90nsfeatures protectasserted on the outputs. The outputs are put in the highagainst inadvertent writes ..
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5962-8859301MPA
Dual Low Offset, Low Power Operational Amplifier
REV. B
Dual Low Offset, Low Power
Operational Amplifier
GENERAL DESCRIPTIONThe OP200 is the first monolithic dual operational amplifier to
offer OP77 type precision performance. Available in the industry-
standard 8-lead pinout, the OP200 combines precision performance
with the space and cost savings offered by a dual amplifier.
The OP200 features an extremely low input offset voltage of less
than 75 µV with a drift below 0.5 µV/°C, guaranteed over the full
military temperature range. Open-loop gain of the OP200 exceeds
5,000,000 into a 10 kΩ load; input bias current is under 2 nA;
CMR is over 120 dB and PSRR below 1.8 µV/V. On-chip
Zener zap trimming is used to achieve the extremely low input
offset voltage of the OP200 and eliminates the need for offset
pulling.
Power consumption of the OP200 is very low, with each amplifier
drawing less than 725 µA of supply current. The total current
drawn by the dual OP200 is less than one-half that of a single
OP07, yet the OP200 offers significant improvements over this
industry-standard op amp. The voltage noise density of the OP200,
11 nV/√Hz at 1 kHz, is half that of most competitive devices.
PIN CONNECTIONS
16-Lead SOIC (S-Suffix)
8-Lead PDIP (P-Suffix)
8-Lead CERDIP (Z-Suffix)
FEATURES
Low Input Offset Voltage: 75 �V Max
Low Offset Voltage Drift, Over –55�C < TA < +125�C:
0.5 �V/�C Max
Low Supply Current (Per Amplifier): 725 �A Max
High Open-Loop Gain: 5000 V/mV Min
Low Input Bias Current: 2 nA Max
Low Noise Voltage Density: 11 nV/√Hz at 1 kHz
Stable with Large Capacitive Loads: 10 nF Typ
Pin Compatible to OP221, MC1458, and LT1013 with
Improved Performance
Available in Die FormFigure 1.Simplified Schematic (One of two amplifiers is shown.)
The OP200 is pin compatible with the OP221, LM158,
MC1458/1558, and LT1013.
The OP200 is an ideal choice for applications requiring multiple
precision op amps and where low power consumption is critical.
For a quad precision op amp, see the OP400.
OP200–SPECIFICATIONS
(VS = ±15 V, TA = 25�C, unless otherwise noted.)ELECTRICAL CHARACTERISTICS*Sample tested.
Specifications subject to change without notice.
OP200
(VS = 15 V, –55�C ≤ TA ≤ +125�C for OP200A, unless otherwise noted.)*Guaranteed by CMR test.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICSNOTESGuaranteed by CMR test.Guaranteed but not 100% tested.
Specifications subject to change without notice.
(VS = �15 V, TA = 25�C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
OP200–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS*Guaranteed by CMR test.
Specifications subject to change without notice.
(VS = ±15 V, –40�C ≤ TA ≤ +85�C, unless otherwise noted.)
ORDERING GUIDE
TA = 25�CFor military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . Continuous
Storage Temperature Range
P, S, Z-Package . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300°C
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP200A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP200E . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
OP200G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
NOTESAbsolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.�JA is specified for worst-case mounting conditions, i.e., �JA is specified for
device in socket for CERDIP and PDIP packages; �JA is specified for device
soldered to printed circuit board for SOIC package.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP200 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Figure 2.Channel Separation Test Circuit
Figure 3.Noise Test Schematic
OP200 TPC 2. Input Offset Voltage
vs. Temperature
TPC 5. Input Bias Current vs.
Common-Mode Voltage
TPC 8. Current Noise Density
vs. Frequency
–Typical Performance Characteristics TPC 1. Warm-Up Drift
TPC 4. Input Offset Current vs.
Temperature
TPC 7. Voltage Noise Density
vs. Frequency
TPC 3. Input Bias Current vs.
Temperature
TPC 6. Common-Mode Rejection
vs. Frequency
TPC 9. 0.1 to 10 Hz Noise
