CD54HC597F3A ,High Speed CMOS Logic 8-Bit Shift Register with Input StorageFeatures Description• Buffered Inputs The ’HC597 and CD74HCT597 are high-speed silicon gateCMOS dev ..
CD54HC597F3A ,High Speed CMOS Logic 8-Bit Shift Register with Input StorageMaximum Ratings” may cause permanent damage to the device. This is a stress only rating and operati ..
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5962-8681701EA-CD54HC597F3A
High Speed CMOS Logic 8-Bit Shift Register with Input Storage
CD54HC597, CD74HC597, CD74HCT597 SCHS191C High-Speed CMOS Logic 8-Bit Shift Register with Input Storage January 1998 - Revised October 2003 Features Description • Buffered Inputs The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 • Asynchronous Parallel Load [ /Title devices. Each device consists of an 8-flip-flop input register (CD74 and an 8-bit parallel-in/serial-in, serial-out shift register. Each • Fanout (Over Temperature Range) register is controlled by its own clock. A “low” on the parallel HC597 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads load input (PL) shifts parallel stored data asynchronously into - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads , the shift register. A “low” master input (MR) clears the shift o o D74 C • Wide Operating Temperature Range . . . -55 C to 125 C register. Serial input data can also be synchronously shifted through the shift register when PL is high. HCT59 • Balanced Propagation Delay and Transition Times 7) Ordering Information • Significant Power Reduction Compared to LSTTL /Sub- Logic ICs o PART NUMBER TEMP. RANGE ( C) PACKAGE ject • HC Types (High CD54HC597F3A -55 to 125 16 Ld CERDIP - 2V to 6V Operation Speed CD74HC597E -55 to 125 16 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CMOS at V = 5V CC CD74HC597M -55 to 125 16 Ld SOIC • HCT Types CD74HC597MT -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation CD74HC597M96 -55 to 125 16 Ld SOIC - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V = 2V (Min) V IL IH CD74HC597NSR -55 to 125 16 Ld SOP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT597E -55 to 125 16 Ld PDIP CD74HCT597M -55 to 125 16 Ld SOIC CD74HCT597MT -55 to 125 16 Ld SOIC CD74HCT597M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC597 (CERDIP) CD74HC597 (PDIP, SOIC, SOP) CD74HCT597 (PDIP, SOIC) TOP VIEW D1 1 16 V CC D2 2 15 D0 D3 3 14 D S D4 4 13 PL D5 5 12 ST CP D6 6 11 SH CP D7 7 10 MR GND 8 9 Q7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
