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54LS74DMQBFN/a5120avaiDual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs


54LS74DMQB ,Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary OutputsFeaturesof the rising edge of the clock. The data on the D input mayYAlternate military/aerospace d ..
54LS85 ,4-Bit Magnitude ComparatorFeaturesgreater length may be compared by connecting compara-YTypical power dissipation 52 mWl keto ..
54LS85DMQB ,4-Bit Magnitude ComparatorsFeaturesgreater length may be compared by connecting compara-YTypical power dissipation 52 mWl keto ..
54S00DM , QUAD 2-INPUT NAND GATE
54S00DM , QUAD 2-INPUT NAND GATE
54S11 , TRIPLE 3-INPUT AND GATE
7016X5 , SMT LEDs 1208 Package Size
70543-0001 , 2.54mm (.100") Pitch SL™ Header, Single Row, Vertical, .120" Pocket, Shrouded, 2Circuits, 0.38μm (15μ") Gold (Au) Selective Plating, Tin (Sn) PC Tail Plating
70553-0106 , 2.54mm (.100") Pitch SL™ Header, Low Profile, Single Row, Right Angle, .120" PocketShrouded, 2 Circuits, 0.76μm (30μ") Gold (Au) Selective Plating, Tin (Sn) PC Tail
70CRU02 ,200V 35A Ultra-Fast Doubler Diode in a TO-218 packageapplications in which the switching energy is designed not to bepredominant portion of the total en ..
70CRU04 ,400V 70A Ultra-Fast Doubler Diode in a TO-218 packageapplications in which the switching energy is designed not to bepredominant portion of the total en ..
70G-IDC5S , Contact Closure DC Input Modules


54LS74DMQB
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
TL/F/6373
54LS74/DM54LS74A/DM74LS74A
Dual
Positive-Edge-Triggered
Flip-Flops
with
Preset,
Clear
and
Complementary
Outputs
June 1989
54LS74/DM54LS74A/DM74LS74A
Dual Positive-Edge-TriggeredD Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
geredD flip-flopswith complementary outputs.The informa-
tionontheD inputis acceptedbythe flip-flopsonthe posi-
tive going edgeof theclock pulse.The triggeringoccursata
voltage levelandisnot directly relatedtothe transition timethe rising edgeofthe clock. The dataontheD input may changed whilethe clockislowor high without affecting
the outputsas longasthe datasetupand hold times arenot
violated.Alow logic levelonthe presetor clear inputswill
setor resetthe outputs regardlessofthe logic levelsofthe
other inputs.
Features Alternate military/aerospace device (54LS74)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6373–1
Order Number 54LS74DMQB, 54LS74FMQB,54LS74LMQB,
DM54LS74AJ, DM54LS74AW,DM74LS74AMor DM74LS74AN
See NSPackage Number E20A, J14A, M14A, N14A orW14B
Function Table
Inputs Outputs CLR CLK D Q Q X X H L X X L H X X H* H* u HH L u LL H L X Q0 Q0eHigh Logic Levele EitherLow orHighLogicLeveleLow Logic Levele Positive-goingTransitionThis configurationis nonstable; thatis,itwillnotpersistwheneitherthe preset
and/or clearinputs returntotheir inactive (high) level.eThe outputlogiclevel ofQbeforethe indicatedinput conditionswere established.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
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