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54LS379
Quad Parallel Register with Enable
TL/F/10186
54LS379/DM74LS379
Quad
Parallel
Register
with
Enable
June 1989
54LS379/DM74LS379
Quad Parallel Register with Enable
General Description
The LS379isa 4-bit register with buffered common Enable.
This deviceis similartothe LS175but features thecommon
Enable rather than common Master Reset.
Features Edge-triggered D-type inputs Buffered positive edge-triggered clock Buffered common enable input Trueand complement outputs
Connection Diagram
Dual-In-Line Package
TL/F/10186–1
Order Number 54LS379DMQB, 54LS379FMQB,
54LS379LMQB, DM74LS379Mor DM74LS379N
SeeNS Package Number E20A,
J16A, M16A, N16Eor W16A
Logic Symbol
TL/F/10186–2
VCCePin16
GNDePin8
Pin DescriptionNames Enable Input (ActiveLOW)
D0–D3 Data Inputs Clock Pulse Input (Active Rising Edge)
Q0–Q3 Flip-FlopOutputs
Q0–Q3 Complement Outputs
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
