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54LS194A
4-Bit Bidirectional Universal Shift Register
TL/F/6407
54LS194A/DM74LS194A
4-Bit
Bidirectional
Universal
Shift
Register
June 1989
54LS194A/DM74LS194A 4-Bit
Bidirectional Universal Shift Register
General Description
This bidirectional shift registeris designedto incorporate
virtuallyallofthe featuresa system designer may wantina
shift register; they feature parallel inputs, parallel outputs,
right-shiftand left-shift serial inputs, operating-mode-control
inputs,anda direct overriding clear line. The registerhas
four distinct modesof operation, namely:
Parallel (broadside) load
Shift right(inthe directionQA towardQD)
Shiftleft(inthe directionQD towardQA)
Inhibit clock(do nothing)
Synchronous parallel loadingis accomplishedby applying
thefourbitsof dataand taking both modecontrol inputs,S0
andS1, high. The datais loadedintothe associatedflip-
flopsand appearatthe outputs afterthe positive transitionthe clock input. During loading, serial data flowis inhibit-
ed.
Shift rightis accomplished synchronously withthe rising
edgeofthe clock pulse whenS0is high andS1is low.
Serial dataforthis modeis enteredatthe shift-right data
input. WhenS0islowandS1is high, data shiftsleft syn-
chronously and new datais enteredatthe shift-left serial
input.
Clockingofthe flip-flopis inhibited when both mode control
inputsare low.
Features Parallel inputsand outputs Four operating modes:
Synchronous parallel load
Right shift
Left shift nothing Positive edge-triggered clocking Direct overriding clear
Connection Diagram
Dual-In-Line Package
TL/F/6407–1
OrderNumber54LS194ADMQB,54LS194AFMQB,
54LS194ALMQB, DM74LS194AMor DM74LS194AN
SeeNS Package Number E20A, J16A, M16A, N16Eor W16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
