DM74LS193N ,Synchronous 4-Bit Binary Counter with Dual ClockFeatures
I Fully independent clear input
I Synchronous operation
I Cascading circuitry pro ..
DM74LS193N ,Synchronous 4-Bit Binary Counter with Dual ClockGeneral Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous ope ..
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54LS193DMQB-DM74LS193N
7 V, synchronous 4-bit up/down binary counter with dual clock
National
Semiconductor
54LS193/DM54LS193/DM74LS193
Synchronous 4-Bit Up/Down Binary
Counters with Dual Clock
General Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so that the outputs change togeth-
er when so instructed by the steering logic. This mode of
operation eliminates the output counting spikes normally as-
sociated with asynchronous (ripple-ciock) counters.
The outputs of the four master-slave flip-ttops are triggered
by a low-to-high level transition of either count (clock) input.
The direction of counting is determined by which count input
is pulsed while the other count input is held high.
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is low. The output will change
independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modify-
ing the count length with the preset inputs.
A clear input has been provided which, when taken to a high
level, forces all outputs to the low level: independent of the
count and load inputs. The clear. count. and load inputs are
buffered to lower the drive requirements of clock drivers,
Me., required for long words.
These counters were designed to be cascaded without the
need for extemai circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underilows.
Similarly, the carry output produces a pulse equal in width to
the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.
Features
a Fully independent clear input
a Synchronous operation
a Cascading circuitry provided internally
:1 Individual preset each flip-flop
I: Alternate Military/Aerospace device (54LS1 93) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor for specifrtrations.
Connection Diagram
Dual-ln-Une Package
INPUTS OUTPUTS INPUTS
f-"---' e---"---,
DATA DATA DATA
lus 15 14 Its
CLEAR BORROW CARRY LOAD C
lu in 10 "
I l 2 3 4
DATA 3 th, tls
ooum coum (1c 0.,
5 s 7 Is
INPUT h-----.' DOWN UP u-----'
OUTPUTS s----.' OUTPUTS
TL/F/6406-1
Order Number 54LS193DMt2B, 64LS193FMt2B, 54LS193LMQB,
DM54LS193d, DM54LS193W, DM74LS193M or DM74LS193N
See NS Package Number E20A, J16A, M16A, N16E or W16A
Absolute Maximum Ratings (Note)
If Mllltary/Aerospace speclfled devlces are required,
please contact the National Semiconductor Sales
Offlttemlatrlttutortt for availability and trpecitlttatluns.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in (he "E/ectika/ Characteristics”
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
DM54LS and 54LS
DM74LS
Storage Temperature Range
_ 55°C to + 125°C
tPC to + 70'C
-65''Cto +150°C
Recommended Operating Conditions
Symbol Parameter DM54LS193 DM74LS193 Unlts
Min Nom Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
" Low Level Input Voltage th? 0.8 V
IOH High Level Output Current --0.4 - 0.4 mA
lot. Low Level Output Current 4 8 mA
tcut Clock Frequency (Note 1) 25 25 MHz
Clock Frequency (Note 2) 0 20 0 20 MHz
tw Pulse Width of Any Input (Note 6) 20 20 ns
tsu Data Setup Time (Note 6) 20 20 ns
tH Data Hold Time (Note 6) 0 0 ns
tREL Release Time (Note 6) 40 40 ns
TA Free Air Operating Temperature - 55 125 0 70 'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Condltlons Mln (N2: 3) Max Units
V. lnputClamp Voltage Vcc = Min, l. = -18 mA -1.5 V
VOH High Level Output Vcc = Min, Iors = Max DM54 2.5 3.4 V
Voltage " = Max, " = Min DM74 2.7 3.4
VOL Low Level Output Vcc = Min, IOL = Max DM54 0.25 0.4
Voltage " = Max,1/iH = Min DM74 0.35 0.5 V
IOL = 4 mA, Vcc = Min DM74 0.25 0.4
l. InputCurrent ti? Max Vcc = Max, lh = 7V 0.1 mA
Input Voltage
IIH High Level InpulCurrent Vcc = Max, VI = 2.7V 20 PA
IIL Low Level lnputCurrent Vcc = Max, V. = 0.4V -0.4 mA
los Short Circuit Vcc = Max DM54 -20 - 100 m A
Output Current (Note 4) DM74 - 20 -100
ICC Supply Current Voc = Max (Note 5) 19 34 mA
Note P. CL = 15 pF, m = 2 kn. IA = 25''C and Vcc = 5v.
Note 2: CL = 50 pF, RL = 2 kn, ls = 25'C and Voc _ 5V.
Note & All typicals are at Vac = 5v. TA = 25'C.
Note W. Not more than one output should be shorted at a lime. and the duration should not exceed one second.
Note 5: log is measured with all outputs open. CLEAR and LOAD inputs grounded, and all other inputs at 4.5V.
Not. 6: TA -- 25'C and Vac --- W,
SBLS'I
Switching Characteristics at Vcc = 5V and TA == 25''C (See Section 1 lorTest Waveforms and Output Load)
RL = 2 kn
From (Input)
Symbol Parameter To (Output) th. = 15 PF th. = 50 PF Units
Min Max Mln Max
fMAx Maximum Clock Frequency 25 20 MHz
tpLH Propagation Delay Time Count Up 26 30 ns
Low to High Level Output to Carry
tPHL Propagation Delay Time Count Up 24 36 n s
High to Low Level Output to Carry
tpLH Propagation Delay Time Count Down 24 29 n tr
Low to High Level Output to Borrow
tpHL Propagation Delay Time Count Down 24 32 ns
High to Low Level Output to Borrow
tpLH Propagation Delay Time Either Count 38 45 ns
Low to High Level Output to Any t2
tpHL Propagation Delay Time Either Count 47 54 n s
High to Low Level Output to Any Q
tpLH Propagation Delay Time Load to 40 41 ns
Low to High Level Output Any a
tpHL Propagation Delay Time Load to 40 47 ns
High to Low Level Output Any 0
tPHL Propagation Delay Time Clear to 35 44 ns
High to Low Level Output Any 0
Logic Diagram
(13) BORROW
00TPOT
(12) CARRY
ourpur
DATA (15)
INPUT A
DOWN (4)
co OUTPUT tta
UP (5)
um (1)
INPUT B
OUTPUT ea
um (10)
INPUT c
om (9)
INPUT i)
cum (1 4)
( ) OUTPU! OD
TL/F/6406-2
86LS‘I
Timing Diagrams
Typical Clear, Load, and Count Sequences
LOAD Ll
c.l 2:22:22:III:IIIIIIIIIIIII22:22:22:XIII:
W i) iIIIIIIIIIIIZIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
c...,.] F. - -- - - ...... -- ..... ..- - -- - -----
0.] :IZIZZIIIZIIZIIIIIIIIIIZIIIIIIIZIIIIIIIIIIIIIIII
C00rlf LFLl"'""Lnf"Ll
0A::::]|__| L l L I l I
"CD, i"-"i.,.;
oc::::1_
OUTPUTS
oo::::1'_
CARRY Ll
BORROW Ll
0 I '13 14 15 0 1 2 I 0 15 14 13
r--"-, -
CLEAR PRESET COUNT UP C' COUNT DOWN
TL/F/6406-3
Not. A: Clear overrides load, data, and count inputs.
Note B.. When counting up, count-down input must be high; when counting down, count-up input must be high,
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
DM54LS193W - product/dm54ls193w?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuIl-wwe
DM54LS193J - product/dm54ls193]?HQS=T|-nulI-nuII-dscatalog-df—pf—nuII-wwe
54LS193LMQB - product/54Is193|mqb?HQS=TI-nu|I—nu||-dscatalog-df—pf—null-wwe
54LS193FMQB - product/54Is193fmqb?HQS=T|-nul|—null-dscatalog-df—pf—nuII-wwe
54LS193DMQB - product/54ls193dmqb?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
DM74LS193M - product/dm74ls193m?HQS=T|-nu|I-nu|I-dscataIog-df-pf-null-wwe
DM74LS193N - product/dm74ls193n?HQS=T|—nu|I-nu|I-dscataIog-df-pf-null-wwe
