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54LS161A-54LS163A
Synchronous 4-Bit Binary Counter with Asynchronous Clear
TL/F/6397
54LS161A/DM54LS161A/DM74LS161A,
54LS163A/DM54LS163A/DM74LS163A
Synchronous
4-Bit
Binary
Counters
May 1992
54LS161A/DM54LS161A/DM74LS161A,
54LS163A/DM54LS163A/DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters featurean inter-
nal carry look-aheadfor applicationin high-speed counting
designs.The LS161Aand LS163A are4-bit binary counters.
The carry outputis decodedby meansofa NOR gate, thus
preventing spikes duringthe normal counting modeof oper-
ation. Synchronous operationis providedby havingallflip-
flops clocked simultaneouslysothatthe outputs changeco-
incident with each other whenso instructedbythe count-
enable inputsand internal gating. This modeof operation
eliminatesthe output counting spikes whichare normally
associated with asynchronous (ripple clock) counters.A
buffered clock input triggersthe four flip-flopsonthe rising
(positive-going) edgeofthe clock input waveform.
These countersare fully programmable;thatis,the outputs
maybe presetto either level.As presettingis synchronous,
settingupalow levelatthe load input disablesthe counter
and causesthe outputsto agree withthe setup data after
the next clock pulse, regardlessofthe levelsofthe enable
input. The clear functionforthe LS161Ais asynchronous;
andalow levelatthe clear input setsallfourofthe flip-flop
outputs low, regardlessofthe levelsof clock, load,oren-
able inputs.The clear functionforthe LS163Ais synchro-
nous;andalow levelatthe clear inputs setsall fourofthe
flip-flop outputslow afterthe next clock pulse, regardlessof
the levelsofthe enable inputs. This synchronous clearal-
lowsthe count lengthtobe modified easily,as decodingthe
maximum count desiredcanbe accomplished withoneex-
ternal NAND gate.Thegate outputis connected tothe clear
inputto synchronously clearthe countertoalllow outputs.
The carry look-ahead circuitry providesfor cascading coun-
tersfor n-bit synchronous applications without additional
gating. Instrumentalin accomplishingthis functionaretwo
count-enable inputsanda ripple carry output.
Both count-enable inputs(PandT) mustbe highto count,
and inputTisfed forwardto enablethe ripple carry output.
The ripplecarry output thusenabledwill producea high-lev- output pulse witha duration approximately equaltothe
high-level portionoftheQA output. This high-level overflow
ripple carrypulsecanbe usedtoenable successive cascad- stages. High-to-low level transitionsatthe enablePorT
inputs may occur, regardlessofthe logic levelofthe clock.
These counters featurea fully independent clock circuit.
Changes madeto control inputs (enablePorTor load)that
will modifythe operating mode haveno effect until clocking
occurs. The functionofthe counter (whether enabled,dis-
abled, loading,or counting)willbe dictated solelybythe
conditions meetingthe stable set-upand hold times.
Features Synchronously programmable Internal look-aheadforfast counting Carry outputfor n-bit cascading Synchronous counting Load controlline Diode-clamped inputs Typical propagation time, clocktoQ output14ns Typical clock frequency32 MHz Typical power dissipation93 mW Alternate Military/Aerospace device (54LS161,
54LS163)is available. Contacta National Semiconduc-
tor Sales Office/Distributorfor specificaitons.
Connection Diagram
Dual-In-Line Package
TL/F/6397–1
Order Numbers 54LS161ADMQB, 54LS161AFMQB,
54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,
54LS163ALMQB, DM54LS161AJ, DM54LS161AW,
DM54LS163AJ, DM54LS163AW, DM74LS161AM,
DM74LS161AN, DM74LS163AMor DM74LS163AN
SeeNS Package Number E20A, J16A,
M16A,N16EorW16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
