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54LS114DMQB.
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
TL/F/10176
54LS114
Dual
Negative
Edge-Triggered
Flip-Flop
with
Common
Clocks
and
Clears
June 1989
54LS114
Dual JK Negative Edge-Triggered
Flip-Flop with Common Clocks and Clears
General Description
The ’LS114 features individualJ,Kandset inputsand com-
mon clockand common clear inputs. Whenthe clock goes
HIGHthe inputsare enabledand datawillbe accepted.The
logic leveloftheJandK inputs maybe allowedto change
whenthe Clock Pulseis HIGHandthe bistablewill perform
accordingtothe truth tableas longasthe minimum setup
timesare observed. Input datais transferredtothe outputsthe negative-going edgeofthe clock pulse.
Connection Diagram
Dual-In-Line Package
TL/F/10176–1
Order Number 54LS114DMQB,
54LS114FMQBor 54LS114LMQB
SeeNS Package Number E20A, J14Aor W14B
Logic Symbol
TL/F/10176–2
VCCePin14
GNDePin7
Pin Names Description
J1,J2,K1,K2 Data Inputs Clock Pulse Input (Active FallingEdge) DirectClear Input (Active LOW)
SD1, SD2 DirectSet Inputs (Active LOW)
Q1,Q2,Q1,Q2 Outputs
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
