54LS109DMQB ,7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary outputFeatures
not directly related to the transition_time of the rising edge of I Altern'ate Military ..
54LS10J ,Triple 3-Input NAND GatesFeaturesYAlternate Military/Aerospace device (54LS10) is avail-Thisdevicecontainsthreeindependentga ..
54LS11 ,Triple 3-Input AND GateFeaturesYAlternate military/aerospace device (54LS11) is avail-Thisdevicecontainsthreeindependentga ..
54LS112 ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OPFeaturesedge of the clock pulse. Data on the J and K inputs may beYAlternate Military/Aerospace dev ..
54LS112DMQB ,7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary outputGeneral Description
This device contains two independent negative-edge-trig-
gered J-K flip-flo ..
54LS114DMQB. ,Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clearsfeatures individual J, K and set inputs and com- when the Clock Pulse is HIGH and the bistable will ..
6S1265R , Power Switch(SPS)
6S1265R , Power Switch(SPS)
6S15658R , Power Switch(SPS)
6SW100M , CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS
6SXB47M , CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS
6SXB47M , CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS
54LS109DMQB
7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output
LS109A
National
Semiconductor
54LS109/ DM54LS109A/DM74Ltt1 09A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-R flip-flops with complementary outputs. The J and
R data is accepted by the fl'rpdlop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of
the clock. The data on the J and R inputs may be changed
while the clock is high or low as long as setup and hold
times are not violated. A low logic level On the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Features
" Alternate Military/Aerospace device (54LS109) is avail.
able. Contact a National Semiconductor Sales Office/
Distributor for spaemcations
Connection Diagram
Dual-ln-Llne Package
Vce cm " i2 cm In: tit fit
ts 15 " 13 12 l,, In ,
y ___9
1 z 3 4 5 s 7 I:
cum n it cut mi til a, sun
TL/FI6368-1
Order Number 64LSt09DMt2B, 54LS109FMOB, DM54L3109AJ,
DM54LS109AW, DM74LS109AM or DMr4LSt09AN
See NS Package Number J16A, M16A. N16E or W16A
Function Table
Inputs Outputs
PR CLR CLK g R o Ft
L H X X X H L
H L X X X L H
L L X X X H* H*
H H t L L L H
H H t H L Toggle_
H H t L H th 00
H H t H H H l
H H L X X 00 00
H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
t = Rising Edge of Pulse
. = This configuration is nonstabie; that is, it will not persist when preset
end/or clear inputs return to their inactive (high) state.
th = The output logic level of a before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each active transition of the clock pulse.
Absolute Maximum Ratings (Note)
If MllltaryfJurrotspamt specified devices are required,
please contact the National Semlttttrtdtmtor Sales
OffltMtftNatrlttutora for avaltablllty and speclflcatlons.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS and 54LS --55'C to + 125°C
DM74LS
Storage Temperature Range
trc to + 70'C
-65'C to +150°C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The de vice should not be operated at these limits. The
parametric values defined In the “Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" tabla Hey/ define
the conditions for actual device operation.
Symbol Parameter DM54LS109A DM74Ls109A Unlts
Mln Nom Max Min Nam Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
Vm High Level Input Voltage 2 2 V
Ihr. Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current -0.4 -0.4 mA
IOL Low Level Output Current 4 8 mA
chK Clock Frequency (Note 2) 25 0 25 MHz
fCLK Clock Frequency (Note 3) 20 0 20 MHz
tw Pulse Width Clock High 18 18
(Note 2) Preset Low 15 15 ns
Clear Low 15 15
tw Pulse Width Clock High 25 25
(Note 3) Preset Low 20 20 ns
Clear Low 20 20
tsu Setup Time Data High 30 t 30 t ns
(Notes 1 & 2) Data Low 20 t 20 t
tsu Setup Time Data High 35 t 35 t ns
(Notos 1 & 3) Data Low 25 t 25 t
tH Hold Time (Note 4) 0 t 0 t ns
TA Free Air Operating Temperature _ 55 125 0 70 "C
Now tt The symbol (T) indicates the rising edge of the clock pulse is used for reference.
Notaz CL - " pF, Rt. = 2 kmn = 251: and vcc = 5V.
Noto 3: cl " so pF, RL '= 2 kn, TA = 25°C and VCC - 5v.
Note 4: TA = 251: and voc = 5v.
VSOI-S'l
LS109A
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Condltlons Min (Note 1) Max Units
VI Input Clamp Voltage Vcc = Min, l. = -18 mA -1.5 V
VOH High Level Output Vcc = Min, '0H = Max DM54 2.5 3.4 V
VOL Low Level Output Vcc = Min, IOL = Max DM54 0.25 0.4
Voltage VIL = Max; W = Min DM74 0.35 0.5 v
lor, = 4 mA, Voc = Min DM74 th25 0.4
I. InputCurrent tit Max Vcc = Max J, R 0.1
InputVoltaga V. = 7V
Clock 0.1 mA
Preset 0.2
Clear 0.2
le, High Level Input Vcc = Max JR 20
Current V. = 2.7V Clock 20
Preset 40
Clear 40
u. Low Level Input Vcc = Max J, R -0.4
Current V. = 0.4V _
Clock 0.4 mA
Preset -0.8
Clear -0.8
los Short Circuit Vcc = Max DM54 -20 -t00 mA
Output Current (Note 2) DM74 -20 - 100
'0c Supply Current Vcc = Max (Note 3) 4 8 mA
Swltchlng Charattterltttles at Vcc = 5V and TA = 25''C (See Section 1 for Test Waveforms and Output Load)
Ri. = 2 kn
From (Input)
Symbol Parameter To (Output) th. = 15 pF A. '= 50 pF Units
Mln Max Mln Max
[MAX Maximum Clock 25 20 MHz
Frequency
tpLH Propagation Delay Time Clock to 25 35 ns
Low to High Level Output Q or G
tPHL Propagation Delay Time Clock to 30 35 ns
High to Low Level Output Q or 6
tpLH Propagation Delay Time Clear
Low to High Level Output to u 25 35 ns
tPHL Propagation Delay Time Clear
High to Low Level Output to Q 30 35 ns
tpLH Propagation Delay Time Preset
Low to High Level Output to o 25 35 ns
tpHL Propagation Delay Time Preset 30 35 ns
High to Low Level Output to Q
Not. tt All typicals are at Vcc - SV, TA = 25’0,
Note 2: Not more than one output should be shorted " a time. and the duration should not exceed one second. For devices. with feedback trom the outputs, where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be pedotmed where vo = 2.25V and 2.125V for DM54 and
DM74 series. respectivety, with the minimum and maximum limit: reduced by one half from their stated values. This is very useful when using automatic test
equipment
Note a Ice ls measured with all outputs open, with CLOCK grounded after setting the a and C outputs high in turn.
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM54LS109AW - product/dm54ls109aw?HQS=T|-nu|I-nuIl-dscataIog-df-pf-null-wwe
54LS109FMQB - product/54Is109fmqb?HQS=T|-nul|-null-dscatalog-df—pf—nuII-wwe
54LS109DMQB - product/54ls109dmqb?HQS=T|-nu|I-nulI-dscatalog-df-pf-nulI-wwe
