54LS109 ,Dual Positive Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary OutputsFeaturesnotdirectlyrelatedtothetransitiontimeoftherisingedgeofYAlternate Military/Aerospace device ..
54LS109DMQB ,7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary outputFeatures
not directly related to the transition_time of the rising edge of I Altern'ate Military ..
54LS10J ,Triple 3-Input NAND GatesFeaturesYAlternate Military/Aerospace device (54LS10) is avail-Thisdevicecontainsthreeindependentga ..
54LS11 ,Triple 3-Input AND GateFeaturesYAlternate military/aerospace device (54LS11) is avail-Thisdevicecontainsthreeindependentga ..
54LS112 ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OPFeaturesedge of the clock pulse. Data on the J and K inputs may beYAlternate Military/Aerospace dev ..
54LS112DMQB ,7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary outputGeneral Description
This device contains two independent negative-edge-trig-
gered J-K flip-flo ..
6S1265R , Power Switch(SPS)
6S1265R , Power Switch(SPS)
6S15658R , Power Switch(SPS)
6SW100M , CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS
6SXB47M , CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS
6SXB47M , CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS
54LS109
Dual Positive Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
TL/F/6368
54LS109/DM54LS109A/DM74LS109A
Dual
Positive-Edge-Triggered
J-K
Flip-Flops
with
Preset,
Clear,
and
Complementary
Outputs
June 1989
54LS109/DM54LS109A/DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
geredJ-K flip-flops with complementary outputs. TheJand datais acceptedbythe flip-floponthe rising edgeofthe
clock pulse.The triggering occursata voltage levelandis
not directly relatedtothe transition timeofthe rising edgeof
the clock.The dataontheJandK inputs maybe changed
whilethe clockis highorlowas longas setup and hold
timesarenot violated.Alow logic levelonthe presetor
clear inputswillsetor resetthe outputs regardlessofthe
logic levelsofthe other inputs.
Features Alternate Military/Aerospace device (54LS109)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications
Connection Diagram
Dual-In-Line Package
TL/F/6368–1
Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,
DM54LS109AW, DM74LS109AMorDM74LS109AN
SeeNS Package NumberJ16A, M16A, N16Eor W16A
Function Table
Inputs Outputs CLR CLK J K QQ X X X H L X X X L H X X X H* H* u LL L H u H L Toggle u LH Q0 Q0 u HH H L L X X Q0 Q0eHigh Logic LeveleLow Logic Levele EitherLoworHigh Logic Levele Rising Edgeof PulseeThis configurationis nonstable;thatis,itwillnot persist when preset
and/orclear inputs returntotheir inactive (high) state.e TheoutputlogiclevelofQ beforethe indicatedinput conditionswere
established.
ToggleeEach output changesto thecomplementofits previous levelon
each active transitionofthe clock pulse.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
