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Partno	Mfg	Dc	Qty	Available	Descript
54FCT273DMQB	NS	N/a	45	avai	Octal D-Type Flip-Flop

54FCT273DMQB ,Octal D-Type Flip-FlopLogic DiagramDS100956-3Please note that this diagram is provided only for the understanding of logi ..
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54FCT374DMQB ,Octal D-Type Flip-Flop with TRI-STATE OutputsLogic DiagramDS100964-3Please note that this diagram is provided only for the understanding of logi ..
54FCT541DMQB ,Octal Buffer/Line Driver with TRI-STATE OutputsElectrical CharacteristicsSymbol Parameter FCT541 Units V ConditionsCCMin Typ MaxV Input HIGH Volta ..
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6MBI100FA-060 ,IGBT MODULEApplications qR5-9-8MUfVf Vi-e Inverter for Motor Drive "u-. OAC, DCtt-m'7r.vy AC'DC Servo Drive ..
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6MBI10L-060 ,IGBT MODULE(600V 10A)Applications 0 Inverter for Motor Drive . AC and DC Servo Drive Amplifier O Uninterruptible ..
6MBI10S-120 ,IGBT MODULE(1200V/10A)Applications· Inverter for motor drive· AC and DC servo drive amplifier· Uninterruptible power sup ..
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54FCT273DMQB
Octal D-Type Flip-Flop
54FCT273
Octal D-Type Flip-Flop
General Description
The ’FCT273has eight edge-triggered D-type flip-flops with
individualD inputs andQ outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs loadand reset
(clear)all flip-flops simultaneously.
The registeris fully edge-triggered. The stateof eachDin-
put, one setup time beforethe LOW-to-HIGH clock transi-
tion,is transferredtothe corresponding flip-flop’sQ output.
All outputswillbe forced LOW independentlyof Clockor
Data inputsbya LOW voltage level onthe MRinput.Thede-
viceis usefulforapplications wherethe trueoutputonlyisre-
quiredandthe Clockand Master Resetare commontoall
storage elements.
Features Eight edge-triggeredD flip-flops Buffered common clock Buffered, asynchronous Master Reset See ’FCT377for clock enable version See ’FCT373for transparent latch version See ’FCT374for TRI-STATE® version Outputsink capabilityof32 mA, source capabilityofmA TTL inputand output level compatible CMOS power consumption Standard Microcircuit Drawing (SMD) 5962-8765601
Ordering Code
Military Package Package Description
Number
54FCT273DMQB J20A 20-Lead Ceramic Dual-In-Line
54FCT273FMQB W20A 20-Lead Cerpack
54FCT273LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, TypeC
Connection Diagrams
Pin Description
Names
D0–D7 Data Inputs Master Reset
(Active LOW) Clock Pulse Input
(Active Rising Edge)
Q0–Q7 Data Outputs
TRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
Pin AssignmentforDIP
and Flatpack
DS100956-1
Pin Assignment
for LCC
DS100956-2
August 1998
54FCT273
Octal
D-T
ype
Flip-Flop 1998 National Semiconductor Corporation DS100956

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