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54FCT273DMQBNSN/a45avaiOctal D-Type Flip-Flop


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54FCT273DMQB
Octal D-Type Flip-Flop
54FCT273
Octal D-Type Flip-Flop
General Description

The ’FCT273has eight edge-triggered D-type flip-flops with
individualD inputs andQ outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs loadand reset
(clear)all flip-flops simultaneously.
The registeris fully edge-triggered. The stateof eachDin-
put, one setup time beforethe LOW-to-HIGH clock transi-
tion,is transferredtothe corresponding flip-flop’sQ output.
All outputswillbe forced LOW independentlyof Clockor
Data inputsbya LOW voltage level onthe MRinput.Thede-
viceis usefulforapplications wherethe trueoutputonlyisre-
quiredandthe Clockand Master Resetare commontoall
storage elements.
Features
Eight edge-triggeredD flip-flops Buffered common clock Buffered, asynchronous Master Reset See ’FCT377for clock enable version See ’FCT373for transparent latch version See ’FCT374for TRI-STATE® version Outputsink capabilityof32 mA, source capabilityofmA TTL inputand output level compatible CMOS power consumption Standard Microcircuit Drawing (SMD) 5962-8765601
Ordering Code
Military Package Package Description
Number

54FCT273DMQB J20A 20-Lead Ceramic Dual-In-Line
54FCT273FMQB W20A 20-Lead Cerpack
54FCT273LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, TypeC
Connection Diagrams
Pin Description
Names

D0–D7 Data Inputs Master Reset
(Active LOW) Clock Pulse Input
(Active Rising Edge)
Q0–Q7 Data Outputs
TRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
Pin AssignmentforDIP
and Flatpack

DS100956-1
Pin Assignment
for LCC

DS100956-2
August 1998
54FCT273
Octal
D-T
ype
Flip-Flop
1998 National Semiconductor Corporation DS100956
ic,good price


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