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54F74FMQB-JM38510/34101SCA
Dual D-Type Positive Edge-Triggered Flip-Flop
TL/F/9469
54F/74F74
Dual
D-Type
Positive
Edge-Triggered
Flip-Flop
December 1994
54F/74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The ’F74isa dual D-type flip-flopwith Direct ClearandSet
inputsand complementary(Q,Q) outputs. Information atthe
inputis transferredtothe outputsonthe positive edgeof
the clock pulse. Clock triggering occursata voltage levelof
the clock pulseandisnot directly relatedtothe transition
timeofthe positive-going pulse. Afterthe Clock Pulse input
threshold voltagehas been passed, theData inputis locked
out and information presentwillnotbe transferredtothe
outputs untilthe next rising edgeofthe Clock Pulse input.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD
makes bothQandQ HIGH
Features Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F74PC N14A 14-Lead (0.300× Wide)Molded Dual-In-Line
54F74DM (Note2) J14A 14-Lead CeramicDual-In-Line
74F74SC (Note1) M14A 14-Lead (0.150× Wide)Molded SmallOutline, JEDEC
74F74SJ (Note1) M14D 14-Lead (0.300× Wide)Molded SmallOutline, EIAJ
54F74FM(Note2) W14B 14-Lead Cerpack
54F74LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note1: Devicesalso availablein13×reel.Use SuffixeSCX.
Note2: Militarygrade device withenvironmentaland burn-in processing.Use suffixe DMQB, FMQBand LMQB.
Logic Symbols
TL/F/9469–3 TL/F/9469–4
IEEE/IEC
TL/F/9469–6
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
