54F64 ,4-2-3-2-Input AND/OR Invert Gate
54F64 ,4-2-3-2-Input AND/OR Invert Gate
54F64 ,4-2-3-2-Input AND/OR Invert Gate
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54F64
4-2-3-2-Input AND/OR Invert Gate
TL/F/9467
54F/74F64
4-2-3-2-Input
AND-OR-Invert
Gate
November 1994
54F/74F64
4-2-3-2-Input AND-OR-Invert Gate
General Description
This device contains gates configuredto performa 4-2-3-2
input AND-OR-INVERT function.
Commercial Military Package Package DescriptionNumber
74F64PC N14A 14-Lead (0.300× Wide)Molded Dual-In-Line
54F64DM (Note2) J14A 14-Lead CeramicDual-In-Line
74F64SC (Note1) M14A 14-Lead (0.150× Wide)Molded SmallOutline, JEDEC
54F64FM(Note2) W14B 14-Lead Cerpack
54F64LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note1: Devicesalso availablein13×reel.Use suffixe SCX.
Note2: Militarygrade device withenvironmentaland burn-in processing.Use suffixe DMQB, FMQBand LMQB.
Logic Symbol
IEEE/IEC
TL/F/9467–3
Connection Diagrams
Pin Assignmentfor
DIP,SOICand Flatpak
TL/F/9467–2
Pin Assignment
for LCC
TL/F/9467–1
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
An,Bn,Cn,Dn Inputs 1.0/1.0 20 mA/b0.6mA Output 50/33.3 b1mA/20mA
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
