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54F379DC
Quad Parallel D Register with Enable
TL/F/9527
54F/74F379
Quad
Parallel
Register
with
Enable
August 1995
54F/74F379
Quad Parallel Register with Enable
General Description
The ’F379isa 4-bit register with buffered common Enable.
This deviceis similartothe ’F175but featuresthe common
Enable rather than common Master Reset.
Features Edge triggered D-type inputs Buffered positive edge-triggered clock Buffered common enable input Trueand complement outputs Guaranteed 4000V minimum ESD protection
Commercial Military Package PackageDescriptionNumber
74F379PC N16E 16-Lead(0.300× Wide) Molded Dual-In-Line
54F379DM(QB) J16A 16-LeadCeramic Dual-In-Line
74F379SC (Note1) M16A 16-Lead(0.300× Wide) Molded Small Outline, JEDEC
74F379SJ(Note1) M16D 16-Lead(0.300× Wide) Molded Small Outline, EIAJ
54F379FM (QB) W16A 16-LeadCerpack
54F379LM(QB) E20A 20-LeadCeramic Leadless ChipCarrier, TypeC
Note1: Devicesalso availablein13×reel.Usesuffixe SCXandSJX.
Logic Symbols
IEEE/IEC
TL/F/9527–5
Connection Diagrams
Pin Assignment
DIP,SOICand Flatpak
TL/F/9527–1
Pin Assignment
for LCC
TL/F/9527–2
TL/F/9527–3
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
