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54F373
Octal Transparent Latch with TRI-STATE Outputs
TL/F/9523
54F/74F373
Octal
Transparent
Latch
with
TRI-STATE
Outputs
May 1995
54F/74F373
Octal Transparent Latch with TRI-STATEÉ Outputs
General Description
The ’F373 consistsof eight latcheswith TRI-STATEoutputs
forbus organized system applications.The flip-flops appear
transparenttothe data when Latch Enable (LE)is HIGH.
WhenLEis LOW,the data that meetsthe setup timesis
latched. Data appearsonthebus whenthe Output Enable
(OE)is LOW. When OEis HIGHthebus outputisinthe high
impedance state.
Features Eight latchesina single package TRI-STATE outputsforbus interfacing Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F373PC N20A 20-Lead(0.300× Wide) Molded Dual-In-Line
54F373DM (QB) J20A 20-LeadCeramic Dual-In-Line
74F373SC (Note1) M20B 20-Lead(0.300× Wide) Molded Small Outline,JEDEC
74F373SJ (Note1) M20D 20-Lead(0.300× Wide) Molded Small Outline,EIAJ
74F373MSA (Note1) MSA20 20-LeadMolded Shrink Small Outline,EIAJ TypeII
54F373FM(QB) W20A 20-LeadCerpack
54F373LM (QB) E20A 20-LeadCeramic Leadless ChipCarrier, TypeC
Note1: Devicesalso availablein13×reel.Use suffixeSCX,SJX,and MSAX.
Logic Symbols Connection Diagrams
IEEE/IEC
TL/F/9523–4
TL/F/9523–1
Pin Assignment
for DIP, SOIC,SSOPand Flatpak
TL/F/9523–2
Pin Assignment
for LCC
TL/F/9523–3
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
