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54F280DC
9-Bit Parity Generator/Checker
TL/F/9512
54F/74F280
9-Bit
Parity
Generator/Checker
August 1995
54F/74F280
9-Bit Parity Generator/Checker
General Description
The ’F280is ahigh-speed parity generator/checkerthatac-
cepts ninebitsof input dataand detects whetheran evenorodd numberof these inputsis HIGH.Ifan even number inputsis HIGH,the Sum Even outputis HIGH.Ifanodd
numberis HIGH,the Sum Even outputis LOW. The Sum
Odd outputisthe complementofthe Sum Even output.
Features Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F280PC N14A 14-Lead (0.300× Wide) Molded Dual-In-Line
54F280DM (Note2) J14A 14-Lead CeramicDual-In-Line
74F280SC (Note1) M14A 14-Lead (0.150× Wide) Molded Small Outline, JEDEC
74F280SJ (Note1) M14D 14-Lead (0.300× Wide) Molded Small Outline, EIAJ
54F280FM(Note2) W14B 14-Lead Cerpack
54F280LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note 1:Devicesalso availablein13×reel. UsesuffixeSCXandSJX.
Note 2:Militarygrade devicewith environmentaland burn-in processing.Use suffixe DMQB, FMQBandLMQB.
Logic Symbols Connection Diagrams
TL/F/9512–3
IEEE/IEC
TL/F/9512–5
Pin Assignmentfor
DIP,SOICand Flatpak
TL/F/9512–1
Pin Assignment
for LCC
TL/F/9512–2
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
