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54F138
1-of-8 Decoder/Demultiplexer
TL/F/9478
54F/74F138
1-of-8
Decoder/Demultiplexer
November 1994
54F/74F138
1-of-8 Decoder/Demultiplexer
General Description
The ’F138isa high-speed 1-of-8 decoder/demultiplexer.
This deviceis ideally suitedfor high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansiontoa 1-of-24 decoder usingjust
three ’F138 devicesora 1-of-32 decoder using four ’F138
devicesandone inverter.
Features Demultiplexing capability Multiple input enablefor easy expansion Active LOW mutually exclusive outputs Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F138PC N16E 16-Lead (0.300× Wide) Molded Dual-In-Line
54F138DM (Note2) J16A 16-Lead CeramicDual-In-Line
74F138SC (Note1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC
74F138SJ (Note1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ
54F138FM(Note2) W16A 16-Lead Cerpack
54F138LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note 1:Devicesalso availablein13×reel. UsesuffixeSCXandSJX.
Note 2:Militarygrade devicewith environmentaland burn-in processing.Use suffixe DMQB, FMQBandLMQB.
Logic Symbols
TL/F/9478–3
IEEE/IEC
TL/F/9478–6
Connection Diagrams
PinAssignment forDIP,
SOICand Flatpak
TL/F/9478–1
Pin Assignment
for LCC
TL/F/9478–2
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
