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54F109DCTIN/a400avaiDual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop


54F109DC ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-FlopFeaturesAsynchronous Inputs:n Guaranteed 4000V minimum ESD protection.LOW input to S sets Q to HIGH ..
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54F109DC
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description

The ’F109 consistsoftwo high-speed, completely indepen-
dent transition clockedJK flip-flops. The clocking operation independentofriseandfall timesofthe clock waveform.
TheJK design allows operationasaD flip-flop (referto ’F74
data sheet)by connectingtheJandK inputs.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQandQ
HIGH
Features
Guaranteed 4000V minimum ESD protection.
Ordering Code:
See Section0
Commercial Military Package Package Description
Number

74F109PC N16E 16-Lead (0.300" Wide) Molded Dual-in-Line
54F109DM (Note2) J16A 16-Lead Ceramic Dual-in-Line
74F109SC (Note1) M16A 16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
74F109SJ (Note1) M16D 16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
54F109FM (Note2) W16A 16-Lead Cerpack
54F109LM (Note2) E20A 16-Lead Ceramic Leadless Chip Carrier, TypeC
Note1:
Devicesalso availablein13"reel.Use suffix= SCXandSJX.
Note2:
Military gradedevicewith environmentaland burn-in processing. Usesuffix= DMQB, FMQBand LMQB.
Logic Symbols

FAST®and TRI-STATE® areregistered trademarksof National SemiconductorCorporation.
DS009471-3 DS009471-4
IEEE/IEC

DS009471-6
November 1994
54F/74F109
Dual
Positive
Edge-T
riggered
Flip-Flop
54F/74F109
1997NationalSemiconductor Corporation DS009471 1
DSXXX
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