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54F08N/a2avaiQuad 2-Input AND Gate


54F08 ,Quad 2-Input AND Gate54F/74F08Quad2-InputANDGateDecember199454F/74F08Quad2-InputANDGateGeneralDescription
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54F08DM ,Quad 2-Input AND GateElectrical CharacteristicsSymbol Parameter 54F/74F Units V ConditionsCCMin Typ MaxV Input HIGH Volt ..
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54F08
Quad 2-Input AND Gate
TL/F/9457
54F/74F08
Quad
2-Input
AND
Gate
December 1994
54F/74F08
Quad 2-Input AND Gate
General Description
This device containsfour independent gates, eachof which
performsthe logic AND function.
Features Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F08PC N14A 14-Lead (0.300× Wide)Molded Dual-In-Line
54F08DM (Note2) J14A 14-Lead CeramicDual-In-Line
74F08SC (Note1) M14A 14-Lead (0.150× Wide)Molded SmallOutline, JEDEC
74F08SJ (Note1) M14D 14-Lead (0.300× Wide)Molded SmallOutline, EIAJ
54F08FM(Note2) W14B 14-Lead Cerpack
54F08LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note1: Devicesalso availablein13×reel.Use suffixeSCXandSJX.
Note2: Militarygrade device withenvironmentaland burn-in processing.Use suffixe DMQB, FMQBand LMQB.
Logic Symbol
IEEE/IEC
TL/F/9457–3
Connection Diagrams
Pin Assignment
for DIP, SOICand Flatpak
TL/F/9457–2
Pin Assignment
for LCC
TL/F/9457–1
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
An,Bn Inputs 1.0/1.0 20 mA/b0.6mA Outputs 50/33.3 b1mA/20mA
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
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