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5497/FMQB
Synchronous Modulo-64 Bit Rate Multiplier
TL/F/9780
5497/DM7497
Synchronous
Modulo-64
Bit
Rate
Multiplier
June 1989
5497/DM7497
Synchronous Modulo-64 Bit Rate Multiplier
General Description
The’97 containsa synchronous 6-stage binary counterand
six decoding gates that serveto gatethe clock throughto
the outputata sub-multipleofthe input frequency.Theout-
put pulserate, relativetothe clock frequency,is determined signals appliedtothe Select (S0–S5) inputs. Bothtrue
and complement outputsare available, alongwithan enable
inputfor each.A Count Enable inputanda Terminal Count
outputare providedfor cascadingtwoor more packages. asynchronous Master Reset input preventscountingand
resetsthe counter.
Connection Diagram
Dual-In-Line Package
TL/F/9780–1
Order Number5497DMQB, 5497FMQBor DM7497N
SeeNS Package Number J16A, N16Eor W16A
Logic Symbol
TL/F/9780–2
VCCePin16
GND ePin8
PinNames Description
S0–S5 Rate Select Inputs OZ EnableInput (Active LOW) OY Enable Input CountEnable Input (ActiveLOW) ClockPulseInput (Active Rising Edge) Asynchronous MasterReset Input (Active HIGH) Gated ClockOutput (Active LOW) Complement Output(ActiveHIGH) Terminal Count Output (Active LOW)
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
