DM74175N ,Hex/Quad D Flip-Flops with Clearfeatures complementary YBuffered clock and direct clear inputsoutputs from each flip-flop.YIndividu ..
DM7417M ,Hex Buffers with High Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM7417N ,Hex Buffers with High Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM74180N ,7 V, 9-bit parity generator/checkerGeneral Description
These universal 9-bit (8 data bits plus 1 parity bit) parity
generators/che ..
DM74181N ,ARITHMETIC LOGIC UNIT/FUNCTION GENERATORSFeatures
I Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magni ..
DM74181N ,ARITHMETIC LOGIC UNIT/FUNCTION GENERATORSapplications data for the DM54S182.
(Continued)
Connection Diagram Pin Designations
Dual-ln-Line ..
DS1744-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
DS1744-70IND ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1744-70IND+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
DS1744P-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744P-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
54174DMQB-54175DMQB-DM54175J-DM74174N-DM74175N
Hex/Quad D Flip-Flops with Clear
TL/F/6557
54174/DM54174/DM74174,
54175/DM54175/DM74175
Hex/Quad
Flip-Flops
with
Clear
June 1989
54174/DM54174/DM74174, 54175/DM54175/DM74175
Hex/QuadD Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry implement D-type flip-flop logic.All havea direct clear
input,andthe quad (175) version features complementary
outputs from each flip-flop.
InformationattheD inputs meetingthe setupand hold time
requirementsis transferredto theQ outputsonthe positive-
going edgeofthe clock pulse. Clock triggering occursata
particular voltage levelandisnot directly relatedtothe tran-
sition timeofthe positive-going pulse. Whenthe clock inputat eitherthe highorlow level,theD input signalhasno
effectatthe output.
Features 174 containssix flip-flops with single-rail outputs 175 contains four flip-flops with double-rail outputs Buffered clockand direct clear inputs Individual data inputto each flip-flop Applications include:
Buffer/storage registers
Shift registers
Pattern generators Typical clock frequency40 MHz Typical power dissipationper flip-flop38 mW Alternate Military/Aerospace device (54174, 54175)is
available. Contacta National Semiconductor SalesOf-
fice/Distributorfor specifications.
Connection Diagrams
Dual-In-Line Package
TL/F/6557–1
Order Number 54174DMQB, 54174FMQB, DM54174J,
DM54174Wor DM74174N
SeeNS Package Number J16A, N16Eor W16A
Dual-In-Line Package
TL/F/6557–2
Order Number 54175DMQB, 54175FMQB,DM54175J,
DM54175Wor DM74175N
SeeNS Package Number J16A, N16EorW16A
Function Table (EachFlip-Flop)
Inputs Outputs
Clear Clock D Q Q² X L H u HH L u LL H X Q0 Q0eHigh Level (steady state)eLow Level (steady state)e Don’tCaree Transitionfrom lowtohighleveleThe levelofQ beforethe indicated steady-stateinput conditionswere established.e175only
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
