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54123DMQBFN/a10avai7 V, dual retriggerable one-shot with clear and complementary output
54123DMQBNSCN/a1avai7 V, dual retriggerable one-shot with clear and complementary output
54123DMQBNSN/a10avai7 V, dual retriggerable one-shot with clear and complementary output


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54123DMQB
7 V, dual retriggerable one-shot with clear and complementary output
National _
Semiconductor
54123/DM74123 Dual Retriggerable One-Shot with
Clear and Complementary Outputs
General Description
The '123 is a dual retriggerable monostable multivibrator
capable of generating output pulses from a few nano-sec-
onds to extremely long duration up to 100% duty cycle.
Each device has three inputs permitting the choice of either
leading-edge or trailing edge triggering. Pin (A) is an active-
low transition trigger input and pin (B) is an active-high tran-
sition trigger input. The clear (CLR) input laminates the out-
put pulse at a predetermined time independent of the timing
components.
National's '123 device features a unique logic realization not
imptemented by other manufacturers, The “Clear" input will
not trigger the device, a design tailored for applications
where it shall only terminate or reduce a timing pulse.
To obtain the best and trauble free operation from this de-
vice please read the operating rules as well as the NSC
one-shot application notes carefully and observe recom-
mendations.
Features
a DC triggered from active-high transition or active-Iow
transition inputs
u Retrlggerable to 100% duty cycle
a Direct reset terminates output pulse
a Compensated for Vcc and temperature variations
" DTL, TTL compatible
" Input clamp diodes
Functional Description
The basic output pulse width is determined by selection of
an external resistor (Fix) and capacitor (Cx). Once triggered,
the basic pulse width may be extended by retriggering the
gated active-low transition or active-high transition inputs or
be reduced by use of the active-low transition clear input.
Retriggering to 100% duty cycle is possible by application of
an input pulse train whose cycle time is shorter than the
output cycie time such that a continuous "HIGH" logic state
is maintained at the "Q" output.
Connection Diagram
Dual-ln-Llne Package Triggering Truth Table
REXT 1 - Inputs R
Voc can con l 01 02 cut 2 82 A2 esponse
A B CLR
lus bs Iu 13 12 lit 10 "
X X L No Trigger
N L X No Trigger
_ X H H Trigger
0 6 cut H f X No Trigger
L f H Trigger
cm r: 0 L H -f- Trigger
H = HIGH Voltage Level
L = LOW Vottage Level
X = Immaterial
I1 I 2 3 4 5 " I 7 "
A1 Bl CLR 1 tht 02 car 2 Rm 2 cup
TL/F/6539-1
Order Number 54123DMt2B, 54123FMQB or DM74123N
See NS Package Number J16A, N16A or WIGA
Absolute Maximum Ratings (Note)
If Mllltary/Aerospace speclfled devlces are required,
please contact the National SemltNmdutttttr Sales
offlttefDltttrlbutora for availability and tttttself/ons.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature
- 55"C to + 125''C
0°C to + 70°C
--65''C to + 150°C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Symbol Parameter 54123 DM74123 Unlts
Mln Nom Max Mln Nom Max
VCC Supply Voltage 4 5 5 5 5 4.75 5 5.25 V
" High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.8 0.8 V
IOH High Level Output Current -0.8 -0.8 mA
IOL Low Level Output Current 16 16 mA
tw Pulse Width A or B High 40
(Note 5) A or B Low 40 ns
Clear Low 40
MS) 1igil','"l't'1gli,t2t Aori3 80 65 ns
REXT External Timing Resistor 5 50 kn
CExr External Timing Capacitance No Restriction WF
Cwmg Wiring Capacitance . 50 pF
at REx-r/CEXT Terminal (Note 5)
TA Free Air Operating Temperature - 55 125 0 70 =
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Mln (N531) Max Unlts
V. Input Clamp Voltage Vcc = Min, II = -12 mA -1.5 V
VOH High Level Output Vcc = Min, IOH = Max 54 2.4 3.4 V
Voltage " == Max,V|H = Min DM74 2.5
VOL Low LevelOutput Vcc = Nlin. lor. = Max 0 2 0.4 V
Voltage VIH == Min, VIL = Max .
k InputCurrent © Max VCC = Max, V; = 5.5V 1 mA
Input Voltage
hr, High Level Input Vcc = Max Data 40 P- A
Current VI = 2.4V Clear 80
ll. Low Level Input Current Vcc == Max, VI = 0.4V Clear -3.2 m A
Data -1.6
los Short Circuit Vcc = Max 54 - 10 ~40 m A
Output Current (Note 2) DM74 _ IO _ 40
'00 Supply Current Vcc = Max (Notes 3 and 4) 46 66 mA
Note t: All Iypicals are at VCC = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: Quiescent Ice is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs opan,CExT = 0.02 pF, and REXT =
25 Kn.
Nate 4: b: is measured in the triggered state with 2.4V applied to all clear and B inputs A inputs grounded, all outputs open. CEXT = 0.02 pF, and REXT = 25 Mt.
Note 5: TA = 25% and Vcc = 5v.
Switching Characteristics at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
100 nA or if stray capacitance from either terminal to
ground is greater than 50 pF the timing equations may
not represent the pulse width the device generates.
2. When an electrolytic capacitor is used for Cx a switching
diode is often required for standard TTL one-shots to pre-
54123 DM74123
From (Input) C = " _ - _
L pF, Rt. - 4000 Ct. - 15 pF, Ri. - 4000.
Symbol Parameter To (Output) CEXT = 0 pF, REXT = 5 kn CEXT = 1000 pF, REXT = " Kn Units
Mln Max Min Max
tpLH Propagation Delay Time
Low to High Level Output A to Q 33 33 ns
tpLH Propagation Delay Time
Low to High Level Output B to Q 28 28 ns
tpHL Propagation Delay Time
High to Low Level Output A to 6 40 40 ns
tPHL Propagation Delay Time
High to Low Level Output B to G 36 36 “5
tpLH Propagation Delay Time
Low to High Level Output Clear to t5 40 40 ns
tpHL Propagation Delay Time t5ltrar
High to Low Level Output lear to O 27 27 ns
twtout) Output Pulse Width" A or B to Cl 3.08 3.76 3.08 3.76 ps
‘CECT --- 1000 tr, REXT = 10 kn
Operating Rules
I. An external resistor (Rx) and external capacitor (Ox) are a a
required for proper operation. The value of Cx may vary I
from 0 to any necessary value. For small time constants 1tre V " , m (7)
high-grade mica. glass, polypropylene, polycarbonate, or h
polystyrene material capacitors may be used. For large l-
time constants use tantalum or special aluminum capaci- --l tG (8)
tors. If the timing capacitors have leakages approaching FIGURE 2 TL/F/6539-3
5. For Cx < 1000 pF see Figure 3 for Tw vs Cx family
curves with Rx as a parameter:
vent high inverse leakage current (Figure a. However, its
use in general is not recommended with retriggerable op-
eration.
3. The output pulse width (T w) for Cx > 1000 pF is defined
as follows:
Tw = K Rx Ox (1 + th7/Rx)
where [Fix is in Kilo-ohm]
[Cx is in pico Farad]
iTw is in nano second]
[K T.5 0.34]
M (II!)
4. The multiplicative factor K is plotted as a function of Cx
below for design considerations:
T|=25°C
Vacs 5.0V
Cut on
FIGURE 3
10 100 1000
TL/F16539-4
6. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
PIN (6) I
TL/ F16539-5
Note: ”Rmmm" should be " ciose to the one-shot as possible.
TL/F/6539-2
TA-25°C
" " It IBJV
g tht "
0 .2 A , .I " 1.21.4 "
'W' COEFFICIENT
FIGURE 1
FIGUHE4
Operating Rules (Continued)
7. The retriggerable pulse width is calculated as shown be-
T=Tw+tpLH=KXRxXCx+tpLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 5).
F--------!
OUIPUT -
TLyF/6539-6
FIGURE 5
8. Output pulse width versus Vcc and Temperatures: Figure
6 depicts the relationship between pulse width variation
versus operating Vcc. Figure 7depicts pulse width varia-
tion versus ambient temperatures.
REXIBSK
CExe10tl0 "
Tet5''0
i5 a "
4 4.5 5 5.5 6
Van: (Vi
TL/F/6539-7
FIGURE 6
Ill T l i
Bm-IDK
Dext-WOOFF
5 Nc vcc-snv a
e 'ss,
-60-30 ll 30 80 ”123150
AHIIENT TEMFEMYUIE Ptll
TL/Ft6539-8
FIGURE 7
Under any operating condition Cx and Rx must be kept
as close to the one-shot device pins as possible to mini-
mize stray capacitance, to reduce noise pick-up, and to
reduce I x R and Ldi/dt voltage developed along their
connecting paths. If the lead length from Cx to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of Cx in each cycle of its
operation so that the output pulse width will be accurate.
The CEXT pins of this device are internally connected to
the internal ground. For optimum system performance
they should be hard wired to the system's return ground
plane.
* However, it should be noted that although the 74221
series one-shot is pin-for-pin compatiable with the
'123 device, its CEXT pin is not an internal connection
to ground. Hence. if substitution of an '221 on to an
'123 design layout whose CEXT pin is wired to the
ground is attempted, the '221 device will not function!
VCC and ground wiring should conform to good high-fre-
quency standards and practices so that switching tran-
sients on the Vcc and ground return leads do not cause
interaction between one-shots A 0.01 yF to 0.10 HF
bypass capacitor (disk ceramic or monolithic type) from
Voc to ground is necessary on each device. Further-
more, the bypass capacitor should be located as close
to the Vcc pin as space permits.
'For further detailed device ttharattterlatitta and output permanence
please refer to the NSC one-shot application note, AN-sse.
This datasheet has been :
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National Semiconductor was acquired by Texas Instruments.
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