47C421ADFVA84 ,CMOS 4-BIT MICROCONTROLLER
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47C421ADFVA84
CMOS 4-BIT MICROCONTROLLER
TOSHIBA
TMM7C221AM,21A
mos 4-BIT MKR0tCONT0R0LLElt
TMM7C221ADF, TMPMEEM ADF
The 47C22tAM21A is a high speed and high performance 4-bit single chip microcomputer with LCD drive
based on the TLCS-d? C MOS series with LCD driver.
PART No. ROM RAM PACKAGE DTP
TMP47C221ADF 2(y48x+ltit 192 I‘v-bit
'hdtt42te8htAty' AthhtlxtVhit 256 14-bit
ClFpiu-P-1d2ijfyOA TMP-d7P421ADF
FEATURES
Op-tyt slngle chip microcomputer
Blragtmoetior, nxncutian time .' 1.9 #5 (atdd Mrtr)
4:59 basic instructions
I Ta tale look-up instructions
Ohuhrou’une nesting ", " levels max,
05 interrupt sources (External : 2, lnternal :4)
All sources have independent latches each, and multiple
interrupt control isauailable.
MID port (28 pins)
. Input 2 ports 5 pin!
a l/tl 6 pans 23 pins
Olnterval Timer
oTwty12-bitTimertCourttert
Tuner. eveM LOUHLET. and pulse widlll mtttrsurttrrumt mud:
¢Serial Inte Hate with d-bit buffer
External t internal clock. and leading Hrailing edge shift
9LCD driver
q LCDdirect drive is abailable (Max, 12-digit display at 114
duty LCD)
o I/d, U3, U2 duties or static drive are programmably
selectable,
9Hold functlon
Battery 1 Capacitor back-up
¢RealTime Emulator: BM4721A + BMAFEBA
QFPiia-PM20-1.tlt)A
FMP47E221ADF
TMP47C42 1 ADF
TMPAYF-SI 1ADF
TUSHMBA
PIN ASSIGNM ENT (TOP VIEW}
QFPEti-PJ 1120- l .0011
TMM7C221AM21 A
EDtrtPM-E2ptftPs4
SEE? -
SEEHJ - am
tptr,TT an:
5:512 - Mil
sun: - m1
SEEM - -fMuly
WD-# WE
$5515 - 'mrs-tra
man! - mm
5551? - MON)
htuIH 'r- - msqm
55519 - 5; n HEW:-
SEG2D - - 'erui"iVlnh0FsdVth m1ctz]
,-rnmqruhurrieaeni---" ._.__._..__
BLOCK DIAGRAM
LCD drnl
supply
Hold input
[5-in-- irspot)
ittyrBt innm
Tait pln
Fftipkd gammy
E-yrtim mntrdlar
Timm; Gnnmamr
flrrtk Generate
y, lr, g F e .- n M 5. -L a
t s'l's'rtii'"'"''9lfi lrl.
U u u u - " c,
'e9rmirrirdrlee nurnu: Emma" drniqutpu:
SE 23 C ML
HH LR "
HM]! trddress buMer
Dam Mammy
Ammulatur
Program
MernDly
STACK Wtt
rrt Tr2 or
llILuIrwl wulluhrr
Interval Timer m-m
Tlmrr-Cuunwr
q-tttt Smal
Intnrfam
"331}. 2
RH RE! R53 m mun“) mam mg
in hy m 'm . R9165] tn
“'EL B90t50 .
Rm nan RSIF Ram manna Ktltl
TCintvt m p-Elrt (Serialpcrt: Input pm
it) port
m [“11 Interrupt 'oput
TOSHIBA
TMP47C221A/421A
PIN FUNCTION
PIN NAME Input/Output FUNCTIONS
K03 to K00 Input 4-bit input port
R43 to R40 . .
4-bit I/O portwith latch.
R53 to R50 When using as input port, the latch must be set to "1" .
R63 to R60 Every bit data is possible to be set, cleared and tested by the manipulation of the
L-register indirect addressing.
R73 to R70
R83 (T1) . . Timer/Counter) external input
............................. 4-bit I/O port with latch. v..........................................................
f.?.2..1N..T..1.). ............ When used as input port, external interrupt oE.1t.try1.i.n..t.tr.r.y1l.i.ryy.t. ...................
R81 (T2) " (Input) input pin, or Timer/Counter external input pin, Timer/Counter 2 external input
............................. the latch must be set to "I ". "r""'""'""."".''""''"''""""'',"".'""''"''"""''""''"''""'""""
R80 (INT2) External interrupt 2 Input
R92 (W) I/OO/O) . . Serial clock I/O
............................................................ 3-bit " port with latch. _........................................................-
R91 (SO) " (Output) When used as input port or serial port, the Serial data output
R90 (S I) l/O (Input) latch must be set to "1". Serial data input
SEG23 to SEGO LCD Segmentdrive output
............................. Output ........‘...................................................................i...........................‘..............................
COM4 to COM1 LCD Common drive output
XIN Input Resonator connecting pin.
XOUT Output For inputting external clock, XIN is used and XOUT is opened.
RESET Input Reset signal input
HOLD (Tm) Input (Input) Hold request/ release signal input Sense input
TEST Input Test pin for out-going test. Be opened or fixed to low level.
VDD + 5 V
VSS Power supply 0 V (GND)
VLC LCDdrive power supply
TOSH I BA TMP47C221A/421A
OPERATIONAL DESCRIPTION
Concerning the 47C221A/421A, the configuration and functions of hardwares are described. As the
description has been provided with priority on those parts differing from the 47C200B/400B, the
technical data sheets for the 47C200B/400B shall also be referred to.
1. SYSTEM CONFIGURATION
o INTERNAL CPU FUNCTION
2.1 Program Memory (ROM)
2.2 Data Memory (ROM)
The others are the same as those of the 47C200B/400B.
o PERIPHERAL HARDWARE FUNCTION
(l) I/O Ports
(2) Interval Timer
© Timer/ Counters (TC1, TC2)
© LCD Driver
S) Serial Interface
The description has been provided with priority on functions (OD, © and (4)) added to and changed
from the 47C200B/400B and ROM / RAM configurations.
2. INTERNAL CPU FUNCTION
2.1 Program Memory (ROM)
Program memory of the 47C221A/421A are similar to the 47C200B/400B except that data conversion
table cannot be used.
2.2 Data Memory (RAM)
Data memory contained in the 47C221A has a 192 x4-bit (addresses 00 to 7FH, C0 to FFH) capacity, and
that contained in the 47C421A has a 256 x4-bit (adddresses 00-FFH) capacity.
There is no physical RAM in address 80-BFH in the 47C221A.
Therefore, when addresses 8O-BFH are accessed on a program, RAM equivalent to address CO-FFH is
accessed.
Address Address
oh, 09H
3 Zero page 5 Zero page
OF ............................... OF ...............................
Data area
Data area
i Image of i
BF address 33
C0 COH - FFH E
i p . : p .
function function
i shared area 3 shared area
(a) 47C221A (b) 47C421A
Figure 2-1. Data Memory Capacity and Address Assignment
TOSH I BA TMP47C221A/421A
3. PERIPHERAL HARDWARE FUNCTION
3.1 l/O port
The 47C221A/421A have 8 I/O .por,ts, (28 pins) each as follows.
C) K0 ' 4- -bitinput
(2) R4, R5, R6, R7 ; 4- bitinput/output
(3) R8 ; 4-bit input/output (shared by external interrupt input and Timer/
Counter input)
(i)) R9 ; 3- bit input/output(shared by serial port)
© KE . l- bit sense input (shared by hold request/release signal input)
For the 47C221A/421A, P1 and' P2 ports are eliminated.
The operations and functions of other ports are similar to that of the 47C200B/400B.
Table 3-1 lists the port address assignments and the I/O instruction that can access the port. Further, the
[OUTB @ HL] instruction and 5-bit to 8-bit data conversion table cannot be used.
Table 3-1. Port Address Assignments and Available I/O Instructions.
port port Input/Output instruction
SET @L
addTESS IN %p,A OUT A, %p CLR @L
OUT #k,%p OUTB @HL SET A’p'b TEST A’p'b
(**) Input (|P**)
Output (OP**)
IN %p,@HL
OUT@HL,%p
CLR %p, b
TESTP %p, b
TEST @L
K0 input port
R4 input port
R5 input port
R6 input port
R7 input port
R8 input port
R9 input port
R4 output port
R5 output port
R6 output port
R7 output port
R8 output port
R9 output port
IOOOOOO
IOOOOOO
IOOOOOO
IOOOOOO
OE SIO, HOLD status
0F Serial receive buffer Serial transmit buffer
10H Undefined Hold operating mode control
11 Undefined — —
12 Undefined — — — — — — — —
13 Undefined — — — - — — — —
14 Undefined —
15 Undefined — — — — — — — —
16 Undefined — _
17 Undefined — —
18 Undefined — —
19 Undefined Interval timer control —
1A Undefined LCDdriver control 1 —
1B Undefined LCD drivercontrol 2 —
1C Undefined Timer/Counter 1 control —
1D Undefined Timer/Counter 2 control —
1E Undefined — —
1F Undefined Serial interface control —
I IOOOOO
Note. "—" means the reserved state. Unavailable for the user programs.
TOSH I BA TMP47C221A/421A
3.2 Timer/Counter (TC1, TC2)
The timer/counter of 47C221A/421A are similer to that of the 47C200B/4OOB except for the following
point. The maximum frequency applied to the external input pin under the event counter mode is
dependent upon the operating state of the LCD drive circuit.
Table 3-2. The maximum frequency applied to the external input pin under the event counter mode.
Maximum frequencyapplied [Hz]
Operating state of the LCD driver I-channel operation 2-channel operation
TC1 TC2 TC1 TC2
At time of blanking operation fc/32 fc/32 fc/40
When LCD display is enabled fc/64 fc/72
Note. fc ;Basic clolck frequency
3.3 LCD Driver
The 47C221A/421A have the circuit that directry drivers the liquid crystal display (LCD) and its control
circuit.
The 42C221/421A have the following connecting pins with LCD.
(O Segment outputpins 24 pins (SEG23-SEG0)
2) Common output pins 4 pins (COM4-COM1)
In addition, VLC pin is provided as the driver power.
The devices that can be directly driven is selectable from LCD of following drive methods.
C) 1/4duty(1/3 bias) LCD ........... Max. 96 segments (8 segmentsx 12 digits)
2) 1/3 duty (1/3 bias) LCD ........... Max. 72 segments (8 segments x 9 digits)
s 1/2duty(1/2 bias) LCD ........... Max. 48 segments (8 segmentsx 6digits)
Cr) Static LCD ...................... Max. 24 segments (8 segments x 3 digits)
3.3.1 Configuration of LCD driver
3 2 1 0 RAM I I
ED'SP D'I'Y Displaydata DAB SLF
OPI B I
I RAM address counter I
' ' fc / 214
Display data select Control l Timing -
e------------------- "
Blanki ng Duty select Control I Control (fl
Control l I
l I I I l I I I I I I I I I I I I I l l I I I
Shift Register
LCD Power Switch , -=al__......j,
& -v Common driver -I Segment driver I
Bias Control I I t
VLC COM4 COMI SEG23 SEGO
Figure 3-1. Configuration of LCD driver
TOSHIBA
TMP47C221A/421A
3.3.2 Control of LCD driver
The LCD driver is controlled by the command register 1, 2 (OP1A, OP1B).
Note that, the MSB of the command register 2 must be cleared to "0" (set to blanking or designation of
driving method) during accessing the command register l.
LCD driver control command register 1
(port address OP1A) (Initial value 1000)
3 2 1 0
DAB SLF
DAB Designation ofdisplay data area
l" 47C221A " l" 47C421A "
000: Reserved Reserved
001: 20-37r, 20-37...
010: 40-57H 40-57H
011: 60-77H 60-77H
100: C0-D7H 80-97H
101: E0-F7H A0-B7H
1 10: Reserved C0-D7H
_111: Reserved E0-F7H
SLF Selection of LCD drive Base frequency
0: M215 [Hz] ...
1: fc/214
Example :
At fc=4.19MHZ
LCD driver control command register 2
(port address OP1B) (Initial value 0000)
EDSP DTY
LCD Display Control
00: Designation ofdriving methods
01: Blanking
10: Reserved
11: LCD display enable
Selection ofdriving methods
00: 1/4 Duty (1/3 Bias)
00: 1/3 Duty (1/3 Bias)
10: 1/2 Duty (1/2 Bias)
11: Static
Basic clock frequency [Hz]
Figure 3-2. LCDdrivercontrolcommandregister
TOSHIBA
TMP47C221A/421A
(1) Driving methods of LCD driver
4 kinds of driving methods can be selected by DTY (bits1 and 0 of command register). Figure 3-3
shows driving waveforms for LCD.
I( > I‘ -l
VLCD l "/fFfl VLCD - l l/h:
o = I- o - ', p l, n TI
i- - J _| - LLIJ L Ll Ll
- VLCD _ VLCD -
l-- Data "1" -l-- Data "0" -1 le Data "I'' _ Data "0" -1
(a) 1/4 Duty (1/3 Bias) Drive (b) 1/3 Duty (1/3 Bias) Drive
I "_ 1 " *I
VLco- I1/fF VLCD - E
o - Ll l Ll o -
- VLCD - - VLCD -
l-I-l _ Data "I'' -il-- Data not! _,|
Data "1" Data "0"
(c) 1/2 Duty (1/2 Bias) Drive (d) Static drive
Note. fr; LCD Frame frequency VLCD; LCD drive voltage (= l/oo-hc)
Figure 3-3. LCD drive wareform (Voltage COM-SEG Pins)
(2) Frame frequency
Frame frequency is set according to the drive method and base frequency as shown in the
following table 3-3.
It is possible to select base frequency (either one of 2 kind frequencies obtained from the driver) by
SLF (bit 0 of command register 1) .
Table 3-3. Setting of LCD frame frequency
Frame Frequency [Hz]
Driving
methods .
Base frequency 1 l4 Duty 1 l3 Duty 1 /2 Duty Static
fc fc 4 fc 4 fc fc
215 215 3 215 2 215 215
Ex. at fc=4.19MHz 128 171 256 128
fc fc 4 fc 4 fc fc
214 214 3 . 214 2 . 214 214
Ex. atfc=2.10MHz 128 171 256 128
Note. fc ,'
Basic clock frequency [Hz]
TOSH I BA TMP47C221A/421A
(3) LCD drive voltage
The LCD drive voltage (VLCD) is given by the difference in potential (VDD - VLC) between pins VDD
and VLC. Therefore, when the CPU operating voltage and LCD drive voltage are the same, the VLC
pin is connected to the VSS pin.
The LCD light only when the difference in potential between the segment output and common
output is i VLcD, and turn off at all other times.
During reset, the power switch of the LCD driver is turned off automatically, shutting off the VLC
voltage.
Both the segment output and common output become VDD level at this time and the LCD turn off.
The power switch is turned on to supply VLC voltage to the LCD driver by setting EDSP (bits 2 and 3
of the command register 2) to "IIs". After that, the power switch will not turn off even during
blanking (setting EDSP to ''01s'') and the VLC voltage continues to flow.
The power switch is turned off during hold operation low power consumption by turning off the
LCD. When hold operation is released the status in effect immediately before the hold operation
is reinstated.
3.3.3LCD display operation
(1) Display data setting
Display data are stored to the display data area (Max.24 words) in the data memory.
The display data area is set using DAB (bits 1 to 3 of command register 1). During reset, the display
data area is set to addresses C0-D7H (47C221A) and 80-97... (47C421A).
The display data stored to the display data area are read automatically and sent to the LCD driver
by the hardware.
The LCD driver generates the segment signals and common signals in accordance with the display
data and drive methods. Therefore, display patterns can be changed by only overwritting the
contents of the display data area with a program. The table look- up instruction is mainly used for
this overwriting. Figure 3-4 shows the correspondence between the display data area and the
SEG/COM pins. The LCD light when the display data is "I " and turn off when "O".
The number of segment which canbe driven differs depending on the LCD drive method,
therefore, the number of display data area bits used to store the data also differs (Refer to Table 3-
4). Consequently, data memory not used to store display data and data memory for which the
addresses are not connected to LCD can be used to store ordinary user's processing data.
Address Bit3 Bit2 Bit1 BitO
32xDAB+00H SEGO
01H SEG1
" 2 02H SE92
32 x DAii+16H 53322
" 17H SEG23 Note. DAB/f to 7
COM4 COM3 COM2 COMl
Figure 3-4. The correspondence between the display data area and the SEG/COM pins
Table 3-4. The data memory bits that are used for driving method and storing display data.
drive methods Bit3 i Bit2 i Bit1 i Bito
1/4 Duty COM4 i COM3 i COM2 é COMl
1/3 D - s COM3 i com i c0M1
1/2 Duty - i - i com i COMI
Static - i - i - é COM1
Note. - / The data memory bits that are not used for storing display data
TOSH I BA TMP47C221A/421A
Transfer ofdisplay data
The display data stored to the display data area are automatically transferred to the LCD driver. The
processing is performed in the following sequence.
C) The LCD driver issues a display data send request to the CPU
© When the instruction (orTimer/Counter processing, interrupt receive processing)
currently being executed is completed, the CPU reads out the data for one cycle and
sends it to the LCD driver.
The data sending cycle is generated when the VLC voltage is being applied to the LCD driver. That
is, after reset is canceled, it is not generated until EDSP is set to "IIB" . Table 3-5 shows the data
sending cycle generation frequency.
When LCD display is enabled, the virtual instruction execution speed drops. For example, when
SLF = 0 and using 1/4 duty drive, this would be 2.05 ps, for an instruction execution speed of 2 ps.
Table 3-5. Frequency of data sending cycle insertion
SLF Driving method Frequency of data sending cycle insertion
0 Static drive 24 times in 1096 instruction cycles
Except Static drive 24 times in 1,024 instruction cycles
1 Static drive 24 times in 2,048 instruction cycles
..... "ici,",','",';";';"':"";,";',",",,'""'""''"""'"'"" "2'rii"d"i"srr'dr2''i"r','s"t'"rrc't'i'"Jn"'c'"y"'c'L"""
Blanking
Blanking is applied by setting EDSP to "013" and turns off the LCD by outputting non light
operation level to the COM pin.
The SEG pin continuously outputs the signal level in accordance with the display data and drive
method. With static drive, no voltage is applied between the COM and SEG pins when the LCD is
turned off by data (display data cleared to "0"), but the COM pin output becomes constant at the
1/Lco/2 level when turning off the LCD by blanking, so the COM and SEG pins are then driven by
l/LCD/il.
3.3.4 Control method of LCD driver
Initial setting
Flow chart of initial setting is shown Figure 3-5.
Example:When operating the 47C421A with 1/4 duty LCD using a Y
frame frequency of fc/215[Hz] (display data area at
addresses 80-97H). Setting of LCD drive method
LD A, #00003; Setsthe1/4dutydrive. l
OUT A, %0P18 fettingofHr.am.efrequycy
LD A, #10008; Setting of base frequency. Setting of Displayareainthe
. . . data memory.
OUT A, %0P1A ; Setting of display area in the
memory.
Setting of clear or initial value of Setting of clyr.or initial value of
. . display area in the data memory,
display area In the memory.
LD A, #11008; Display enable(Release of Displayyyyblt
blanking) (Release of blanking)
OUT A, %0PlB
Figure 3-5. Initial setting of
LCD driver
TOSHIBA
TMP47C221A/421A
(2) Displaydata setting
Normally, display data are kept permanently in the program memory and are then stored to the
display data area by the table look up instruction.
This can be explained using numberical display with 1/4 duty LCD as an example. The COM and SEG
connections to the LCD are the same as those shown in Figure 3-6, and the display data are as shown in
Table 3-6. Programming example for displaying numerals corresponding to BCD data stored at address
10H in the data memory is shown below. The display data area is at addresses 20H and 21H.
LO HL, #OFCH ;Tosetthe DC
LO A, 10H
ST A, @HL+
ST #DTBL/16, @HL+
ST #DTBL/256,@HL+
LO HL, #20H ;Displayofdata corresponding
LOL A, (il0C
ST A, OHL+
LDH A, (iloc+
ST A, @HL+
DTBL: DATA 110111118, 000001108, COMI
111000113, 101001118, ti' COM2
001101103, 101101013,
111101013, 000101118, (Ei/aC-C,?,
111101113, 101101118 SEGO erty..,Acos4
Figure 3-6. Example of COM and SEG
connections
Table 3-6. Examples of Display Data (1/4 Duty LCD)
mNeth Display Display data memory mNelgl Display Display data memory
Upper Lower Upper Lower
0 g; 1101 1111 5 E”? 1011 0101
1 g 0000 0110 6 f g 1111 0101
_'",'',',',',',) i
2 I 1110 0011 7 g 0001 0111
J,L) LY
3 g 1010 0111 8 t g 1111 0111
4 g 0011 0110 9 g 1011 0111
TOSHIBA
TMP47C221A/421A
Table 3-7 shows the same numerical display used in Table 3-6, but using 1/2 duty LCD. The connections of
the COM and SEG pins to the LCD are the same as those shown in Figure 3-7. The display data area is at
addresses 20-23H.
LO HL, #OFCH ; Tosetthe DC
LO A, 10H
ST A, @HL+
ST #DTBL/16, 0HL+
ST #OTBL/256,0HL+
LO HL, #ZOH l Displayofdatacorresponding
LDL A, (i)OC
ST A, @HL+
RORC A
RORC A
ST A, @HL+
LDH A, (iloc+
ST A, 0HL+
RORC A COMI
RORC A , COM2
ST A, @HL+ 366? com
DATA 01110111B, 001000108, SEGO 'it:ctYtcot-rn4
100101113, 101001113, SEG1
111000103, 111001013,
111101018, 011000113, Figure 3-7. Example_ofCOM and SEG
111101118, 11100111B connections
Table 3-7. Example of Display Data (1/2 duty LCD)
Display data memory Display data memory
Nu- Nu-
meral Upper Lower meral Upper Lower
o **01 H11 um “11 5 H11 H10 **01 **01
1 **00 M10 H00 H10 6 H11 H11 **01 **01
2 **10 M01 **01 M11 7 **01 M10 **00 M11
3 H10 H10 **01 **11 8 H11 H11 um **11
4 **11 M10 H00 H10 9 H11 H10 **01 **11
Note. *; don't care
(3) Example ofdrive output
@0— £0
gz: Mo
Q SEGO
Display data memory _I_|_I-——I_I—l—— .— VDD
covvn '
Address
20H 0101
21 1011
_— VDD
'J_I _ VLCD
|_I [—1 l_| l_—| |_I '
COM1—SEGO |_| |_| LJ |_| |_ _ 0
(Selected) _| I I
' VLCD
I—-I F'Il—1l—'
_l |_qu-0
COM3 — SEG1
(Non — Selected)
- VLCD
Figure 3-8. 1/4Duty (1 /BBias) Drive
[é SEGO COM1 fl
U 0 w 0
EDSP ——|—
SEG" _l—l_|—|_l_|_l—I_I_U_ '— VD”
SEG1 I .— VDD
Display data memory
Add ress
SEGZ —L—I_|—l—|_|_l-— I
20H *010
21 *111
COW _l_l—I—I_l—l— : DD
22 **O1
, — VDD
d0” 1‘ “"9 c0M2_|_|_I_|—I_l—|_l—I__ :
_— VDD
COM3 -_ VLC
I—I _ VLCD
COMl—SEG1 I _ 0
(Selected) I I I
— VLCD
I——I l—I '
L_I |___0
Note *,'
' VLCD
COMZ — SEGZ
(Non — Selected) —'l
- VLCD
Figure 3—9. 1/3Duty (1 /BBias) Drive
f___________
SE63 j E El SEGO
WB 05%
SEGO —‘ _ _ VDD
SEG1 —‘ _ VDD
Display data memory _ VLC
Address
— _VLC
*t01 SE63
22 — VLC
23 M1‘!
CORA1____J L___J
Note *; don’t care
.—'_| 7
_| I—l_‘ *—'
__ VLC
COM1 — SEG1
(Selected)
COM1 — SEGZ
(Non — Selected)
Figure 3-10. 1/2 Duty (1 /ZBias) Drive
Display data memory
Add ress
SEGO VDD
***0 VLC
SEG4 VDD
***0 VDD
***1 VDD
Note *;
don ’t care
COM1 — SEGO 0
(Selected)
- VLCD
COM1 — SEG4 '— 0
(Non — Selected)
- VLCD
Figure 3-11. Static Drive
TOSH I BA TMP47C221A/421A
INPUT/ OUTPUT CURCUITRY
(1) Control pins
Input/Output circuitries of the 47C221A/421A control pins are similarto that of the 47CZOOB/4OOB.
(2) I/O Ports
The input/output circuitries of the 47C221A/421A I/O ports are shown below, any one of the
circuitries can be chosen by a code (GA-GF) as a mask option.
PORT " INPUT/OUTPUT CIRCUITRY and CODE REMARKS
GA, GD GB, GE GC, GF
pull-up/pull-down
R resistor
KO Input R RIN
:1 H“ El R RIN RIN = 70 kn(typ0
R = 1k§2(typ.)
GA, GB, GC GD, GE, GF
Initial "Hi-Z" Initial "High" VDD Sink open drain or
ush- ullout ut
R4 p p p
R6 R = 1 kn (typ.)
Sink open drain
-C>o-l output
R7 I/O R Initial "Hi-Z"
R = 1 kn (typ.)
Sink open drain
output
R8 Initial "Hi-Z"
Hysteresis input
R = 1 kn (typ.)
TOSH I BA TMP47C221A/421A
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Vss = 0 V)
PARAM ETER SYMBOL PINS RATING UNIT
Supply Voltage VDD -0.5to7 V
Supply Voltage (LCD drive) VLC - 0.5 to VDD + 0.5 V
Input Voltage VIN -0.5 to VDDt0.5 V
VouT1 Except sink opendrain pin -0.5 to VDD+O.5
Output Voltage V
Voure Sink opendrain pin -0.5 to 10
Output Current (per1 pin) IOUT 3.2 mA
Power Dissipation [Topr = 70°C] PD 400 mW
Soldering Temperature (time) Tsld 260 (10 s) T
Storage Temperature Tstg - 55 to 125 T
Operating Temperature Topr - 30 to 70 T
RECOMMENDED OPERATING CONDITIONS (Vss = 0 V, Topr = - 30 to 70 "C)
PARAMETER SYMBOL PINS CONDITIONS Min. Max. UNIT
In the Normal
operating mode 4.5 V
Supply Voltage VDD In the Hold 6.0
operating mode 2.0
V|H1 Except Hysteresis Input VDD x 0.7
VDD24.5 V V
Input High Voltage VIHz Hysteresis Input VDD x 0.75 DD V
VIH3 VDD<4.5V VDDx0.9
VIL1 Except Hysteresis Input VDD x 0.3
. VDD24.5 v
Input Low Voltage VILZ Hysteresis Input 0 VDD x 0.25 V
V|L3 VDD<4.5 v VDDx 0.1
Clock Frequency fc 0.4 4.2 MHz
Note 1. Input Voltage ViH3, VIL3 : in the HOLD operating mode.
Note 2. 1MHz is recommended as minimum freqency when SLF = 1. And 2MHz is when SLF=0.
TOSHIBA
TMP47C221A/421A
D.C. CHARACTERISTICS
Nss = 0 V, VDD = 4.5 to 6.0 V, Topr = - 30 to 70 °C)
PARAM ETER SYMBOL PINS CONDITIONS Min. Typ. Max. UNIT
HysteresisVoltage VH3 Hysteresis Input - th7 - V
Port K0, TEST, W,
|IN1 HOLD 1/DD=5.5V,
Input Current - - + 2 PA
IINZ PortsR(open drain) VIN=5.5V/0V
Low Input Current IIL Ports R (push-pull) VDD = 5.5 V, " = 0.4 V - - - 2 mA
Port K0 with pull-up/pull-
. RIN1 down resistor 30 70 150
Input Resistance kn
RINZ RESET 100 220 450
Output Leakage .
Current lco Ports R (open drain) VDD = 5.5 V, VOUT = 5_5 V - - 2 PA
Output High Voltage VoH Ports R (push-pull) VDD = 4.5 V, IOH -- - 200 ssA 2.4 i i V
Output Low Voltage VOL; Except XOUT VDD = 4.5 V, IOL = 1.6 mA - - 0.4 V
Segment Output Low .
Resistance Ros, SEG pm
Common Output Low . - 10 -
Resistance Rom COM pln
Segment Output High . kn
Resistance R052 SEG pm
Common Output High . - 70 -
Resistance R0C2 COM pln VDD = 5 V. VDD - VLc = 3 V
V02/3 3.8 4.0 4.2
Segment/Common
Vo1/2 SEG /COM pin 3.3 3.5 3.7 V
Output Voltage
Vo1/3 2.8 3.0 3.2
SupplyCurrent VDD-- 5.5V, VLC-- Vss
(in the Normal mode) 'DD fc=4MHz - 3 6 mA
Supply Current -
(in the HOLD mode) 'DDH VDD‘5'5V - 0.5 10 PA
Note 1. Typ. values show those at Top, --25 "C, VDD = 5 V.
Note2. Input Current IIN1 : The current through resistor is not included, when the input resistor (pull-up
/puII-down) is contained.
Note3. Output resistance Ros, Roc : indicates the on resistance during level switching.
Note4. Voz/3 : indicates 2/3 level output voltage when driving at 1/4 or 1/3 duty.
Note5. Vo1/2 : indicates 1/2 level output voltage for 1/2 duty orstatic drive.
Note6. Vo1/3 : indicates 1/3 level output voltage when driving at 1/4 or 1/3 duty.
Note7. Supply Current: VIN =5.3 V/ 0.2 V.
The voltage applied to the port R is within the valid range VIL or VIH.
Note 8. When using LCD, it is necessary to consider values ofRosv2 and Roc1/2-
Note 9. Times for SEG/ COM output resistance switching on .'
Rose, Roc1 : 2/fs (s)
Rosa, Roca: Il(rvfr)
(1/n : duty, fr: frame frequency)
TOSH I BA TMP47C221A/421A
A.C. CHARACTERISTICS Nss = 0 V, VDD = 4.5 to 6.0 V, Topr = - 30 to 70 "C)
PARAMETER SYMBOL CONDITIONS Min. Typ. Max. UNIT
Instruction Cycle Time tcy IS - 20 MS
High level Clock pulse Width twcH
External clock mode 80 - - ns
Low level Clock pulse Width tWCL
Shift data Hold Time tSDH 0.5 tcy-BOO - - ns
Note. Shift data Hold Time:
External circuit forsik pin and SO pin Serial port (completion of transmission)
m 1.5 V
350'" so x x x As,
RECOMMENDED OSCILLATING CONDITIONS (Vss = 0 V: VDD = 4.5 to 6.0 V, Topr = - 30 to 70 °C)
XIN XOUT
(1) 4 MHz
Ceramic Resonator
CSA4.00MG (MURATA) CXIN = CXOUT = 30 pF 4 MHz
KBR-4.00MS (KYOCERA) CXIN = CXQUT = 30 pF
. CXIN CXOUT
Crystal Oscillator 7; JI)
204B-6F 4.0000 (TOYOCOM) CXIN = Cxou'r = 20 pF
(2) 400 kHz XIN XOUT
Ceramic Resonator
CSB4OOB (MURATA) CXIN = CXOUT = 220 pF, RXOUT = 6.8 kn R
KBR-AOOB (KYOCERA) cxm = CXOUT = 100 pF, RXOUT =10 kn 400 kHz XOUT
"tlt" g CXOUT
TOSHIBA
TMP47C221A/421A
TYPICAL CHARACTERISTICS
R R - Ta K0 port
(kn) VDD = 5.5 v
100 /;
/ www''''
- 40 0 40 80 (°C)
IOH - VOH CMOS R port
(#A) ""'s VDD = 4.5 V
Ta = 25 "C
- 400 "s,
- 200 l
- 100 "
2 4 6 (V)
lor - VOL R port
(mA) VDD = 4.5 V
Ta = 25 ''C
0.4 0.8 1.2 (V)
'00 - VDD
(mA) Ta = 25 °c
fc-4MHz
3 5 7 (V)
R - Ta RESET pin
(kn) VDD = 5.5 v
w.,,.,.--"'"
200 -''"'
- 40 0 40 80 (°C)
IIC-VIN CMOSRport
A VDD = 5.5 v
:30) Ta = 25 T
- "'"ss
- 600 N
- 400 .
- 200 l
2 4 6 (V)
IOL - VOL P1, P2 port
(mA) VDD = 4.5 V
Ta = 25 "C
20 _,,,,""
0.4 0.8 1.2 (V)
'00 - fc Operating area
IDD fc
VDD=5.5V Ta= -30to70T
(mA) Ta = 25 "C (MHz (Normal mode)
1 // 2
0 fc 0 Voo
0.1 0.4 1 4 10 (MHz) 2 4 6 (V)
(sNh ; LCD operation)
Note. 1 MHz is recommended as minimum freqency when SLF= 1. And2 MHz is when SLF=0.
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