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2N7002F ,TrenchMOS(tm) Logic Level FET
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2N7002F
TrenchMOS(tm) Logic Level FET
2N7002F renchMOS™ Logic Level FET
Rev. 01 — 11 February 2002 Product dataM3D088
DescriptionN-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
2N7002F in SOT23.
Features TrenchMOS™ technology Very fast switching Logic level compatible Subminiature surface mount package.
Applications Relay driver High speed line driver Logic level translator.
Pinning information TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
Table 1: Pinning - SOT23, simplified outline and symbol gate (g)
SOT23 source (s) drain (d)
Philips Semiconductors 2N7002F
TrenchMOS™ Logic Level FET Quick reference data Limiting values
Table 2: Quick reference dataVDS drain-source voltage (DC) Tj =25to150°C - 60 V drain current (DC) Tsp =25 °C; VGS=10V - 475 mA
Ptot total power dissipation Tsp =25°C - 0.83 W junction temperature - 150 °C
RDSon drain-source on-state resistance VGS=10 V; ID= 500 mA; Tj=25 1.7 2 Ω
VGS= 4.5 V; ID=75 mA; Tj=25 2.25 4 Ω
Table 3: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage (DC) Tj =25to150°C - 60 V
VDGR drain-gate voltage (DC) Tj =25to150 °C; RGS =20kΩ -60 V
VGS gate-source voltage (DC) - ±30 V
VGSM peak gate-source voltage tp≤50 μs; pulsed; duty cycle= 25% - ±40 V drain current (DC) Tsp =25 °C; VGS =10V; Figure2 and3 - 475 mA
Tsp= 100 °C; VGS =10V; Figure2 - 300 mA
IDM peak drain current Tsp =25 °C; pulsed; tp≤10 μs; Figure3 - 1.9 A
Ptot total power dissipation Tsp =25 °C; Figure1 - 0.83 W
Tstg storage temperature −65 +150 °C operating junction temperature −65 +150 °C
Source-drain diode source (diode forward) current (DC) Tsp =25°C - 475 mA
ISM peak source (diode forward) current Tsp =25 °C; pulsed; tp≤10μs - 1.9 A
Philips Semiconductors 2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors 2N7002F
TrenchMOS™ Logic Level FET Thermal characteristics
7.1 Transient thermal impedance
Table 4: Thermal characteristicsRth(j-sp) thermal resistance from junction to solder point mountedona metal clad board; Figure4- - 150 K/W
Rth(j-a) thermal resistance from junction to ambient mounted on a printed circuit board;
minimum footprint - 350 K/W
Philips Semiconductors 2N7002F
TrenchMOS™ Logic Level FET Characteristics
Table 5: Characteristics =25 °C unless otherwise specified
Static characteristicsV(BR)DSS drain-source breakdown voltage ID =10 μA; VGS =0V =25°C 6075- V= −55°C 55 --V
VGS(th) gate-source threshold voltage ID=1 mA; VDS =VGS; Figure9 =25°C 12- V= 150°C 0.6 - - V= −55°C - - 3.5 V
IDSS drain-source leakage current VDS =48V; VGS =0V =25°C - 0.01 1.0 μA= 150°C --10 μA
IGSS gate-source leakage current VGS= ±15 V; VDS=0V - 10 100 nA
RDSon drain-source on-state resistance VGS=10 V; ID= 500 mA; Figure7 and8 =25°C - 1.7 2 Ω= 150°C - - 3.7 Ω
VGS= 4.5 V; ID =75mA; Figure7 and8 =25°C - 2.25 4 Ω
Dynamic characteristicsgfs forward transconductance VDS =10V; ID= 200 mA 100 300 - mS
Ciss input capacitance VGS =0V; VDS=10 V; f=1 MHz; Figure11 - 2540pF
Coss output capacitance - 18 30 pF
Crss reverse transfer capacitance - 7.5 10 pF
ton turn-on time VDD =50V; RD= 250 Ω; VGS =10V; =50 Ω; RGS =50Ω 3 10 ns
toff turn-off time - 1215ns
Source-drain diodeVSD source-drain (diode forward) voltageIS= 300 mA; VGS =0V; Figure12 - 0.85 1.5 V
trr reverse recovery time IS= 300 mA; dIS/dt= −100 A/μs; VGS =0V;
VDS =25V
-30 - ns recovered charge - 30 - nC
Philips Semiconductors 2N7002F
TrenchMOS™ Logic Level FET
