29F040 ,4 Mbit 512Kb x8 / Uniform Block Single Supply Flash MemoryLogic DiagramERASE SUSPEND and RESUME MODESLOW POWER CONSUMPTION– Read mode: 8mA typical (at 12MHz) ..
29F040C-55 , 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 5V ONLY EQUAL SECTOR FLASH MEMORY
29F52 ,8-Bit Registered Transceiver (Inverting)
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29F040
4 Mbit 512Kb x8 / Uniform Block Single Supply Flash Memory
Figure 1. Logic Diagram
M29F0404 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory
NOT FOR NEW DESIGN
M29F040 is replaced by the M29F040B5V ± 10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
BYTE PROGRAMMING TIME: 10μs typical
ERASE TIME Block: 1.0 sec typical Chip: 2.5 sec typical
PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte Data Polling and T oggle bits Protocol for
P/E.C. Status
MEMORY ERASE in BLOCKS 8 Uniform Blocks of 64 KBytes each Block Protection Multiblock Erase
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION Read mode: 8mA typical (at 12MHz) Stand-by mode: 25μA typical Automatic Stand-by mode
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION Defectivity below 1ppm/year
ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: E2h
Table 1. Signal NamesNovember 1999 1/31
Figure 2B. TSOP Pin Connections
Figure 2A. LCC Pin Connections
Figure 2C. TSOP Reverse Pin Connections DESCRIPTIONThe M29F040 is a non-volatile memory that may
be erased electrically at the block level, and pro-
grammed Byte-by-Byte.
The interface is directly compatible with most mi-
croprocessors. PLCC32 and TSOP32 (8 x 20mm)
packages are available. Both normal and reverse
pin outs are available for the TSOP32 package.
OrganisationThe Flash Memory organisation is 512K x8 bits with
Address lines A0-A18 and Data Inputs/Outputs
DQ0-DQ7. Memory control is provided by Chip
Enable, Output Enable and Write Enable Inputs.
Erase and Program are performed through the
internal Program/Erase Controller (P/E.C.).
Data Outputs bits DQ7 and DQ6 provide polling or
toggle signals during Automatic Program or Erase
to indicate the Ready/Busy state of the internal
Program/Erase Controller.
Memory BlocksErasure of the memory is in blocks. There are 8
uniform blocks of 64 Kbytes each in the memory
address space. Each block can be programmed
and erased over 100,000 cycles. Each uniform
block may separately be protected and unpro-
2/31
M29F040
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. Depends on range.
Table 2. Absolute Maximum Ratings (1)
tected against program and erase. Block erasure
may be suspended, while data is read from other
blocks of the memory, and then resumed.
Bus OperationsSeven operations can be performed by the appro-
priate bus cycles, Read Array, Read Electronic
Signature, Output Disable, Standby, Protect Block,
Unprotect Block, and Write the Command of an
Instruction.
Command InterfaceCommand Bytes can be written to a Command
Interface (C.I.) latch to perform Reading (from the
Array or Electronic Signature), Erasure or Pro-
gramming. For added data protection, command
execution starts after 4 or 6 command cycles. The
first, second, fourth and fifth cycles are used to
input a code sequence to the Command Interface
(C.I.). This sequence is equal for all P/E.C. instruc-
tions. Command itself and its confirmation - if it
applies - are given on the third and fourth or sixth
cycles.
InstructionsSeven instructions are defined to perform Reset,
Read Electronic Signature, Auto Program, Block
Auto Erase, Chip Auto Erase, Block Erase Suspend
and Block Erase Resume. The internal Pro-
gram/Erase Controller (P/E.C.) handles all timing
and verification of the Program and Erase instruc-
tions and provides Data Polling, T oggle, and Status
data to indicate completion of Program and Erase
Operations.
Instructions are composed of up to six cycles. The
first two cycles input a code sequence to the Com-
mand Interface which is common to all P/E.C.
instructions (see T able 7 for Command Descrip-
tions). The third cycle inputs the instruction set up
command instruction to the Command Interface.
Subsequent cycles output Signature, Block Protec-
tion or the addressed data for Read operations.
For added data protection, the instructions for pro-
gram, and block or chip erase require further com-
mand inputs. For a Program instruction, the fourth
command cycle inputs the address and data to be
programmed. For an Erase instruction (block or
chip), the fourth and fifth cycles input a further code
sequence before the Erase confirm command on
the sixth cycle. Byte programming takes typically
10μs while erase is performed in typically 1.0 sec-
ond.
Erasure of a memory block may be suspended, in
order to read data from another block, and then
resumed. Data Polling, Toggle and Error data may
be read at any time, including during the program-
ming or erase cycles, to monitor the progress of
the operation. When power is first applied or if VCC
falls below VLKO, the command interface is reset to
Read Array.
3/31
M29F040
Note: X = VIL or VIH
Table 3. Operations
Table 4. Electronic Signature
Note: SA = Address of block being checked
Table 5. Block Protection Status
DEVICE OPERATION
Signal Descriptions
Address Inputs (A0-A18). The address inputs forthe memory array are latched during a write opera-
tion. The A9 address input is used also for the
Electronic Signature read and Block Protect veri-
fication. When A9 is raised to VID, either a Read
Manufacturer Code, Read Device Code or Verify
Block Protection is enabled depending on the com-
bination of levels on A0, A1 and A6. When A0, A1
and A6 are Low, the Electronic Signature Manufac-
turer code is read, when A0 is High and A1 and A6
are Low, the Device code is read, and when A1 is
High and A0 and A6 are low, the Block Protection
Status is read for the block addressed by A16, A17,
A18.
Data Input/Outputs (DQ0-DQ7). The data input isa byte to be programmed or a command written to
the C.I. Both are latched when Chip Enable E and
Write Enable W are active. The data output is from
the memory Array, the Electronic Signature, the
Data Polling bit (DQ7), the Toggle Bit (DQ6), the
Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-
puts are valid when Chip Enable E and Output
Enable G are active. The output is high impedance
when the chip is deselected or the outputs are
disabled.
Chip Enable (E). The Chip Enable activates thememory control logic, input buffers, decoders and
sense amplifiers. E High deselects the memory and
reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Addresses are then
latched on the falling edge of E while data is latched
on the rising edge of E. The Chip Enable must be
forced to VID during Block Unprotect operations.
Output Enable (G). The Output Enable gates theoutputs through the data buffers during a read
operation. G must be forced to VID level during
Block Protect and Block Unprotect operations.
Write Enable (W). This input controls writing to theCommand Register and Address and Data latches.
Addresses are latched on the falling edge of W, and
Data Inputs are latched on the rising edge of W.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
4/31
M29F040
Notes:1. Command not interpreted in this table will default to read array mode. While writing any command or during RSG and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I. X = Don’t Care. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output
Device code. Protection Address: A0, A6 at VIL, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection
status. Address bits A15-A18 are don’t care for coded address inputs. Optional, additional blocks addresses must be entered within a 80μs delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. Read Data Polling or Toggle bit until Erase completes.
10. A wait time of 5μs is necessary after a Reset command, if the memory is in a Block Erase status, before starting
any operation.
Table 6. Instructions (1,2)5/31
M29F040
Memory BlocksThe memory blocks of the M29F040 are shown in
Figure 3. The memory array is divided in 8 uniform
blocks of 64 Kbytes. Each block can be erased
separately or any combination of blocks can be
erased simultaneously. The Block Erase operation
is managed automatically by the P/E.C. The opera-
tion can be suspended in order to read from any
other block, and then resumed.
Block Protection provides additional data security.
Each uniform block can be separately protected or
unprotected against Program or Erase. Bringing A9
and G to VID initiates protection, while bringing A9,
G and E to VID cancels the protection. The block
affected during protection is addressed by the in-
puts on A16, A17, and A18. Unprotect operation
affects all blocks.
OperationsOperations are defined as specific bus cycles and
signals which allow Memory Read, Command
Write, Output Disable, Standby, Read Status Bits,
Block Protect/Unprotect, Block Protection Check
and Electronic Signature Read. They are shown in
Tables 3, 4, 5.
Read. Read operations are used to output the
contents of the Memory Array, the Status Register
or the Electronic Signature. Both Chip Enable E
and Output Enable G must be low in order to read
the output of the memory. The Chip Enable input
also provides power control and should be used for
device selection. Output Enable should be used to
gate data onto the output independent of the device
selection. The data read depends on the previous
command written to the memory (see instructions
RST and RSIG, and Status Bits).
Write. Write operations are used to give InstructionCommands to the memory or to latch input data to
be programmed. A write operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the rising
edge of W or E whichever occurs first.
Output Disable. The data outputs are high imped-ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and Program/Erase Controller
P/E.C. is Idle. The power consumption is reduced
to the standby level and the outputs are high im-
pedance, independent of the Output Enable G or
Write Enable W inputs.
Automatic Standby. After 150ns of inactivity andwhen CMOS levels are driving the addresses, the
chip automatically enters a pseudo standby mode
where consumption is reduced to the CMOS
standby value, while outputs are still driving the
bus.
Electronic Signature. Two codes identifying themanufacturer and the device can be read from the
memory, the manufacturer’s code for STMicroelec-
tronics is 20h, and the device code is E2h for the
M29F040. These codes allow programming equip-
ment or applications to automatically match their
interface to the characteristics of the particular
manufacturer’s product. The Electronic Signature
is output by a Read operation when the voltage
applied to A9 is at VID and address inputs A1 and
A6 are at Low. The manufacturer code is output
when the Address input A0 is Low and the device
code when this input is High. Other Address inputs
are ignored. The codes are output on DQ0-DQ7.
This is shown in Table 4.
The Electronic Signature can also be read, without
raising A9 to VID by giving the memory the instruc-
tion RSIG (see below).
Block Protection. Each uniform block can beseparately protected against Program or Erase.
Block Protection provides additional data security,
as it disables all program or erase operations. This
mode is activated when both A9 and G are set to
VID and the block address is applied on A16-A18.
Block Protection is programmed using a Presto F
program like algorithm. Protection is initiated on the
edge of W falling to VIL. Then after a delay of 100μs,
the edge of W rising to VIH ends the protection
operation. Protection verify is achieved by bringing
G, E and A6 to VIL while W is at VIH and A9 at VID.
Under these conditions, reading the data output will
yield 01h if the block defined by the inputs on
A16-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the
device.
Any protected block can be unprotected to allow
updating of bit contents. All blocks must be pro-
tected before an unprotect operation. Block Un-
protect is activated when A9, G and E are at VID.
The addresses inputs A6, A12, A16 must be main-
tained at VIH. Block Unprotect is performed through
a Presto F Erase like algorithm. Unprotect is initi-
ated by the edge of W falling to VIL. After a delay
of 10ms, the edge of W rising to VIH will end the
unprotection operation. Unprotect verify is
achieved by bringing G and E to VIL while A6 and
W are at VIH and A9 at VID. In these conditions,
reading the output data will yield 00h if the block
defined by the inputs on A16-A18 has been suc-
cessfully unprotected. All combinations of A16-
A18 must be addressed in order to ensure that all
of the 8 uniform blocks have been unprotected.
Block Protection Status is shown in Table 5.
6/31
M29F040
Figure 3. Memory Map and Block Address Table
Table 7. CommandsInstructions and CommandsThe Command Interface (C.I.) latches commands
written to the memory. Instructions are made up
from one or more commands to perform Read
Array/Reset, Read Electronic Signature, Block
Erase, Chip Erase, Program, Block Erase Suspend
and Erase Resume. Commands are made of ad-
dress and data sequences. Addresses are latched
on the falling edge of W or E and data is latched
on the rising of W or E. The instructions require from
1 to 6 cycles, the first or first three of which are
always write operations used to initiate the com-
mand. They are followed by either further write
cycles to confirm the first command or execute the
command immediately. Command sequencing
must be followed exactly. Any invalid combination
of commands will reset the device to Read Array.
The increased number of cycles has been chosen
to assure maximum data security. Commands are
initialised by two preceding coded cycles which
unlock the Command Interface. In addition, for
Erase, command confirmation is again preceeded
by the two coded cycles.
P/E.C. status is indicated during command execu-
tion by Data Polling on DQ7, detection of Toggle on
DQ6, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output those four
bits. The P/E.C. automatically sets bits DQ3, DQ5,
DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and
DQ4) are reserved for future use and should be
masked.
7/31
M29F040
Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Table 8. Status Register
Data Polling bit (DQ7). When Programming op-erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid only effective during P/E.C. operation, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at the address being programmed or at an address
within the block being erased. If the byte to be
programmed belongs to a protected block the com-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100μs, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms.
Toggle bit (DQ6). When Programming operationsare in progress, successive attempts to read DQ6
will output complementary data. DQ6 will toggle
following toggling of either G or E when G is low.
The operation is completed when two successive
reads yield the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing. The toggle bit is valid only effective during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the byte to be programmed belongs to a
protected block the command will be ignored. If the
blocks selected for erasure are protected, DQ6 will
toggle for about 100μs and then return back to
Read. See Figure 11 for Toggle Bit flowchart and
Figure 12 for Toggle Bit waveforms.
Error bit (DQ5). This bit is set to ’1’ by the P/E.Cwhen there is a failure of byte programming, block
erase, or chip erase that results in invalid data
being programmed in the memory block. In case of
error in block erase or byte program, the block in
which the error occured or to which the pro-
grammed byte belongs, must be discarded. Other
blocks may still be used. Error bit resets after Reset
(RST) instruction. In case of success, the error bit
will set to ’0’ during Program or Erase and to valid
data after write operation is completed.
8/31
M29F040
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
Note:1. Sampled only, not 100% tested.
Table 10. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Erase Timer bit (DQ3). This bit is set to ’0’ by theP/E.C. when the last Block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the wait period is
finished, after 80 to 120μs, DQ3 returns back to ’1’.
Coded Cycles. The two coded cycles unlock theCommand Interface. They are followed by a com-
mand input or a comand confirmation. The coded
cycles consist of writing the data AAh at address
5555h during the first cycle and data 55h at address
2AAAh during the second cycle. Addresses are
latched on the falling edge of W or E while data is
latched on the rising edge of W or E. The coded
cycles happen on first and second cycles of the
command write or on the fourth and fifth cycles.
Read Array/Reset (RST) instruction. The Resetinstruction consists of one write operation giving
the command F0h. It can be optionally preceded
by the two coded cycles. A wait state of 5μs before
read operations is necessary if the Reset command
is applied during an Erase operation.
Read Electronic Signature (RSIG) instruction.This instruction uses the two coded cycles followed
by one write cycle giving the command 90h to
address 5555h for command setup. A subsequent
read will output the manufacturer code, the device
code or the Block Protection status depending on
the levels of A0, A1, A6, A16, A17 and A18. The
manufacturer code, 20h, is output when the ad-
dresses lines A0, A1 and A6 are Low, the device
code, E2h is output when A0 is High with A1 and
A6 Low.
Table 9. AC Measurement Conditions9/31
M29F040
Table 11. DC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)
Read Block Protection (RBP) instruction. Theuse of Read Electronic Signature (RSIG) command
also allows access to the Block Protection status
verify. After giving the RSIG command, A0 and A6
are set to VIL with A1 at VIH, while A16, A17 and
A18 define the block of the block to be verified. A
read in these conditions will output a 01h if block is
protected and a 00h if block is not protected.
This Read Block Protection is the only valid way to
check the protection status of a block. Neverthe-
less, it must not be used during the Block Protection
phase as a method to verify the block protection.
Please refer to Block Protection paragraph.
Chip Erase (CE) instruction. This instruction usessix write cycles. The Erase Set-up command 80h
is written to address 5555h on third cycle after the
two coded cycles. The Chip Erase Confirm com-
mand 10h is written at address 5555h on sixth cycle
after another two coded cycles. If the second com-
mand given is not an erase confirm or if the coded
cycles are wrong, the instruction aborts and the
device is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing to FFh. Read
operations after the sixth rising edge of W or E
output the status register bits. During the execu-
tion of the erase by the P/E.C. the memory accepts
only the Reset (RST) command. Read of Data
Polling bit DQ7 returns ’0’, then ’1’ on completion.
The Toggle Bit DQ6 toggles during erase operation
and stops when erase is completed. After comple-
tion the Status Register bit DQ5 returns ’1’ if there
has been an Erase Failure because the erasure
has not been verified even after the maximum
number of erase cycles have been executed.
10/31
M29F040
Notes:1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
Table 12A. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3)
Block Erase (BE) instruction. This instructionuses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two coded cycles. The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
the block to be erased is given and latched into the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequently to erase other blocks in parallel, without
further coded cycles. The erase will start after an
Erase timeout period of about 100μs. Thus, addi-
tional Block Erase commands must be given within
this delay. The input of a new Block Erase com-
mand will restart the timeout period. The status of
the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C
is erasing the block(s). Before and during Erase
timeout, any command different from 30h will abort
the instruction and reset the device to read array
mode. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register bits.
During the execution of the erase by the P/E.C., the
memory accepts only the ES (Erase Suspend) and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The T oggle Bit DQ6 toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure because erasure has not completed even
after the maximum number of erase cycles have
been executed. In this case, it will be necessary to
input a Reset (RST) to the command interface in
order to reset the P/E.C.
11/31
M29F040
Notes:1. Sampled only, not 100% tested. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
Table 12B. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)
Program (PG) instruction. The memory can beprogrammed Byte-by-Byte. This instruction uses
four write cycles. The Program command A0h is
written on the third cycle after two coded cycles. A
fourth write operation latches the Address on the
falling edge of W or E and the Data to be written
on its rising edge and starts the P/E.C. During the
execution of the program by the P/E.C., the mem-
ory will not accept any instruction. Read operations
output the status bits after the programming has
started. The status bits DQ5, DQ6 and DQ7 allow
a check of the status of the programming operation.
Memory programming is made only by writing ’0’ in
place of ’1’ in a Byte.
Erase Suspend (ES) instruction. The Block
Erase operation may be suspended by this instruc-
tion which consists of writing the command 0B0h
without any specific address code. No coded cycles
are required. It allows reading of data from another
block while erase is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution and defaults to read array mode. Writing
this command during Erase timeout will, in addition
to suspending the erase, terminate the timeout.
The Toggle Bit DQ6 stops toggling when the P/E.C.
is suspended. Toggle Bit status must be monitored
at an address out of the block being erased. Toggle
Bit will stop toggling between 0.1μs and 15μs after
the Erase Suspend (ES) command has been writ-
ten.
The M29F040 will then automatically set to Read
Memory Array mode. When erase is suspended,
Read from blocks being erased will output invalid
data, Read from block not being erased is valid.
During the suspension the memory will respond
only to Erase Resume (ER) and Reset (RST) in-
structions. RST command will definitively abort
erasure and result in the invalid data in the blocks
being erased.
12/31
M29F040
Figure 6. Read Mode AC Waveforms13/31
M29F040
Note:1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
Table 13A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2)
Erase Resume (ER) instruction. If an Erase Sus-pend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
coded cycles.
Power UpThe memory Command Interface is reset on power
up to Read Array. Either E or W must be tied to VIH
during Power-up to allow maximum security and
the possibility to write a command on the first rising
adge of E or W. Any write cycle initiation is blocked
when VCC is below VLKO.
Supply RailsNormal precautions must be taken for supply volt-
age decoupling, each device in a system should
have the VCC rail decoupled with a 1.0μF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
14/31
M29F040
Note:1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
Table 13B. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)
15/31
M29F040
Figure 7. Write AC Waveforms, W Controlled
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.16/31
M29F040
