29F010 Fast Delivery |IC PHOENIX CO.,LIMITED

29F010 ,1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only / Uniform Sector Flash MemoryLogic Diagram, and Table 1, SignalA 0.1μF capacitor should be connected betweenNames, for a brief o ..
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29F010
1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only / Uniform Sector Flash Memory
1/20
PRELIMINARY DATA
July 1999
M29F010B Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory SINGLE 5V±10% SUPPLY VOLTAGEfor
PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 45ns PROGRAMMING TIME
–8μsper Byte typical8 UNIFORM16 Kbytes MEMORY BLOCKS PROGRAM/ERASE CONTROLLER Embedded Byte Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLESper
BLOCK 20 YEARS DATA RETENTION Defectivity below1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 20h
TSOP32(N)x 20mm
PLCC32(K)
PDIP32(P)
Figure1. Logic Diagram
AI02735
A0-A16
DQ0-DQ7
VCC
M29F010B
VSS
M29F010B
2/20
Figure2A. PLCC Connections
AI02737
A13
A10
DQ5
DQ0
DQ1DQ2 DQ3DQ4
A16
DQ7
A12
A14V
M29F010B
A15
A11
DQ6
Figure2B. TSOP Connections
DQ0 A3
A13
A10
DQ7
A14
A11 G
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A16
A12
VCC
A15
AI02738
M29F010B8 17
VSS
Figure2C. PDIP Connections
DQ0
A13
A10
DQ7
A14
A11
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6A16
A12 VCC
A15
AI02736
M29F010B8
Table1. Signal Names
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs/Outputs Chip Enable Output Enable Write Enable
VCC Supply Voltage
VSS Ground Not Connected Internally
SUMMARY DESCRIPTION
The M29F010Bisa1 Mbit (128Kbx8) non-volatile
memory that canbe read, erased and repro-
grammed. These operations canbe performedus-
inga single5V supply.On power-upthe memory
defaultstoits Read mode whereit canbe readin
the same wayasa ROMor EPROM.
The memoryis divided into blocks that canbe
erased independentlysoitis possibleto preserve
3/20
M29F010B
valid data whileold datais erased. Each block can protected independentlyto prevent accidental
Programor Erase commands from modifyingthe
memory. Program and Erase commandsare writ-
tentothe Command Interfaceofthe memory.An
on-chip Program/Erase Controller simplifies the
processof programmingor erasingthe memoryby
taking careofallofthe special operations thatare
requiredto updatethe memory contents. The enda programor erase operation canbe detected
and any error conditions identified. The command
set requiredto controlthe memoryis consistent
with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operationof the memory.
They allow simple connectionto most micropro-
cessors, often without additional logic.
The memoryis offeredin PLCC32, TSOP32(8x
20mm) and PDIP32 packages. Access timesof
45ns, 70ns, 90ns and 120nsare available. The
memoryis supplied withallthe bits erased (setto
’1’).
SIGNAL DESCRIPTIONS
See Figure1, Logic Diagram, and Table1, Signal
Names,fora brief overviewofthe signals connect-tothis device.
Address Inputs (A0-A16). The Address Inputs
selectthe cellsinthe memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sentto the
Command Interfaceofthe internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The DataIn-
puts/Outputs outputthe data storedatthe selected
address duringa Bus Read operation. During Bus
Write operations they represent the commands
senttothe Command Interfaceofthe internal state
machine.
Chip Enable (E). The Chip Enable,E, activates
the memory, allowing Bus Readand Bus Writeop-
erationstobe performed. When Chip Enableis
High, VIH,all other pinsare ignored.
Output Enable (G). The Output Enable,G, con-
trolsthe Bus Read operationofthe memory.
Write Enable (W). The Write Enable,W, controls
the Bus Write operationof the memory’s Com-
mand Interface.
VCC Supply Voltage. The VCC Supply Voltage
suppliesthe powerforall operations (Read, Pro-
gram, Erase etc.).
The Command Interfaceis disabled whenthe VCC
Supply Voltageis less thanthe Lockout Voltage,
VLKO. This prevents Bus Write operations fromac-
cidentally damaging the data during power up,
power down and power surges.If the Program/
Erase Controlleris programmingor erasing during
this time thenthe operation aborts andthe memo- contents being alteredwillbe invalid. 0.1μF capacitor shouldbe connected between
the VCC Supply Voltagepin andthe VSS Ground
pinto decouplethe current surges fromthe power
supply. The PCB track widths mustbe sufficientto
carry the currents required during program and
erase operations, ICC4.
Vss Ground. The VSS Groundis the reference
forall voltage measurements.
Table2. Absolute Maximum Ratings(1)
Note:1. Exceptforthe rating ”Operating Temperature Range”, stresses above those listedinthe Table ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stressratingsonlyand operationofthe deviceat theseorany other conditions
above those indicated inthe Operating sectionsofthis specificationisnot implied. Exposureto Absolute Maximum Rating condi-
tions forextended periods mayaffect device reliability. Referalso totheSTMicroelectronics SURE Programand other relevantqual-
ity documents. Minimum Voltagemay undershootto–2V during transition andforlessthan 20ns during transitions.
Symbol Parameter Value Unit
Ambient Operating Temperature (Temperature Range Option1) 0to70 °C
Ambient Operating Temperature (Temperature Range Option6) –40to85 °C
Ambient Operating Temperature (Temperature Range Option3) –40to125 °C
TBIAS Temperature Under Bias –50to125 °C
TSTG Storage Temperature –65to150 °C
VIO(2) Inputor Output Voltage –0.6to6 V
VCC Supply Voltage –0.6to6 V
VID Identification Voltage –0.6to 13.5 V
M29F010B
4/20
Table3. Block Addresses
Size (Kbytes) Address Range 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 00000h-03FFFh
BUS OPERATIONS
Therearefive standard bus operations that control
the device. Theseare Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table4, Bus Operations,fora summary. Typically
glitchesof less than 5nson Chip Enableor Write
Enableare ignoredbythe memory anddonotaf-
fect bus operations.
Bus Read. Bus Read operations read from the
memory cells,or specific registersin the Com-
mand Interface.A valid Bus Read operationin-
volves settingthe desired addressonthe Address
Inputs, applyinga Low signal, VIL,to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputswill outputthe
value, see Figure7, Read ModeAC Waveforms,
and Table11, ReadAC Characteristics,for details whenthe output becomes valid.
Bus Write. Bus Write operations writeto the
Command Interface.A valid Bus Write operation
beginsby settingthe desired addressonthe Ad-
dress Inputs. The Address Inputsare latchedby
the Command Interfaceonthe falling edgeof Chip
Enableor Write Enable, whichever occurs last.
The Data Inputs/Outputsare latchedbythe Com-
mand Interfaceonthe rising edgeof Chip Enable Write Enable, whichever occurs first. OutputEn-
able must remain High, VIH, duringthe whole Bus
Write operation. See Figures8 and9, WriteAC
Waveforms, and Tables12 and 13, Write AC
Characteristics,for detailsofthe timing require-
ments.
Output Disable. The Data Inputs/Outputsarein
the high impedance state when Output Enableis
High, VIH.
Standby. When Chip Enableis High, VIH, the
Data Inputs/Outputs pinsare placedinthe high-
impedance state and the Supply Currentisre-
ducedtothe Standby level.
When Chip EnableisatVIHthe Supply Currentis
reducedtothe TTL Standby Supply Current ICC2. further reducethe Supply Currenttothe CMOS
Standby Supply Current, ICC3, Chip Enable should held within VCC± 0.2V. For Standby current
levels see Table10,DC Characteristics.
During programor erase operationsthe memory
will continueto use the Program/Erase Supply
Current, ICC4,for Programor Erase operationsun-
tilthe operation completes.
5/20
M29F010B
Table4. Bus Operations
Note:X=VILorVIH.
Operation E G W Address Inputs Data
Inputs/Outputs
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH XHi-Z
Standby VIH XX X Hi-Z
Read Manufacturer
Code VIL VIL VIH A0= VIL,A1= VIL,A9=VID,
OthersVILorVIH 20h
Read Device Code VIL VIL VIH A0= VIH,A1= VIL,A9=VID,
OthersVILorVIH 20h
Automatic Standby.If CMOS levels (VCC± 0.2V)
are usedto drivethe bus andthe busis inactivefor
150nsor more the memory enters Automatic
Standby wherethe internal Supply Currentisre-
ducedtothe CMOS Standby Supply Current, ICC3.
The Data Inputs/Outputswillstill output dataifa
Bus Read operationisin progress.
Special Bus Operations
Additional bus operations canbe performedto
read the Electronic Signature and alsoto apply
and remove Block Protection. These bus opera-
tionsare intendedfor useby programming equip-
ment and are not usually usedin applications.
They requireVIDtobe appliedto some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that canbe readto identify the memory.
These codes canbe readby applyingthe signals
listedin Table4, Bus Operations.
Block Protection and Blocks Unprotection. Each
block canbe separately protected against acci-
dental Programor Erase. Protected blocks canbe
unprotectedto allow datatobe changed. Block
Protection and Blocks Unprotection operations
must onlybe performedon programming equip-
ment.For further information referto Application
Note AN1122, Applying Protection and Unprotec-
tionto M29 Series Flash.
M29F010B
6/20
COMMAND INTERFACE
All Bus Write operationstothe memoryare inter-
pretedby the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations. Failureto observea valid sequenceof Bus
Write operationswill resultinthe memory return-
ingto Read mode. The long command sequences
are imposedto maximize data security.
The commandsare summarizedin Table5, Com-
mands. Referto Table5in conjunction withthe
text descriptions below.
Read/Reset Command. The Read/Reset com-
mand returnsthe memorytoits Read mode where behaves likea ROMor EPROM.It also resets
the errorsin the Status Register. Either oneor
three Bus Write operations canbe usedto issue
the Read/Reset command. the Read/Reset commandis issued duringa
Block Erase operationor followinga Programming Erase error thenthe memorywill take upto 10μs abort. Duringthe abort periodno valid data can read fromthe memory. Issuinga Read/Reset
command duringa Block Erase operation will
leave invalid datainthe memory.
Auto Select Command. The Auto Select com-
mandis usedto readthe Manufacturer Code,the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations arere-
quiredto issuethe Auto Select command. Once
the Auto Select commandis issuedthe memory
remainsin Auto Select mode until another com-
mandis issued.
From the Auto Select mode the Manufacturer
Code canbe read usinga Bus Read operation
withA0=VIL andA1= VIL. The other address bits
maybesetto eitherVILor VIH. The Manufacturer
Codefor STMicroelectronicsis 20h.
The Device Code canbe read usinga Bus Read
operation withA0=VIH andA1= VIL. The other
address bits maybesetto eitherVILor VIH.The
Device Codeforthe M29F010Bis 20h.
The Block Protection Statusof each block canbe
read usinga Bus Read operation withA0= VIL,= VIH, and A14-A16 specifyingthe addressof
the block. The otheraddress bits maybesettoei-
therVIL orVIH.Ifthe addressed block isprotected
then 01his outputonthe Data Inputs/Outputs, oth-
erwise 00his output.
Program Command. The Program command
canbe usedto programa valueto one addressin
the memory arrayata time. The commandre-
quires fourBus Write operations,the final writeop-
eration latchesthe address and data inthe internal
state machine and startsthe Program/Erase Con-
troller.the address fallsina protected block then the
Program commandis ignored,the data remains
unchanged. The Status Registeris never read and error conditionis given.
Duringthe program operationthe memorywillig-
noreall commands.Itisnot possibleto issue any
commandto abortor pausethe operation. Typical
program timesare givenin Table6. Bus Readop-
erations duringthe program operationwill output
the Status Registeronthe Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
After the program operation has completed the
memorywill returntothe Read mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read mode.
Note thatthe Program command cannot changea
bitsetat’0’ backto’1’ and attemptingtodosowill
causean error. Oneofthe Erase Commands must usedtosetallthebitsina blockorinthe whole
memory from’0’to’1’.
Unlock Bypass Command. The Unlock Bypass
commandis usedin conjunction withthe Unlock
Bypass Program commandto programthe memo-
ry. Whenthe access timetothe deviceis long(as
with some EPROM programmers) considerable
time saving canbe madeby using these com-
mands. Three Bus Write operationsare required issuethe Unlock Bypass command.
Oncethe Unlock Bypass command has beenis-
suedthe memorywill only acceptthe Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory canbe readasifin
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command canbe usedto
program one addressin memoryata time. The
command requires two Bus Write operations,the
final write operation latchesthe address and datathe internal state machine and startsthe Pro-
gram/Erase Controller.
The Program operation usingthe Unlock Bypass
Program command behaves identicallytothe Pro-
gram operation using the Program command.A
protected block cannotbe programmed;the oper-
ation cannotbe aborted andthe Status Registeris
read. Errors mustbe reset usingthe Read/Reset
command, which leavesthe devicein UnlockBy-
pass Mode. Seethe Program commandfor detailsthe behavior.
7/20
M29F010B
Table5. Commands
Note:X Don’t Care,PA Program Address,PD Program Data,BAAny addressinthe Block.
All valuesinthetablearein hexadecimal.
The Command Interfaceonlyuses addressbits A0-A10to verifythe commands,the upper addressbitsare Don’t Care.
Read/Reset.Aftera Read/Reset command,readthe memoryas normaluntil another commandis issued.
Auto Select.AfteranAuto Select command,read ManufacturerID, DeviceIDor Block Protection Status.
Program, Unlock Bypass Program,Chip Erase, Block Erase.After these commandsreadthe Status Registeruntilthe Program/Erase
Controller completesandthe memory returnsto Read Mode.Add additional Blocks during Block Erase Commandwith additionalBus Write
Operationsuntilthe TimeoutBitisset.
Unlock Bypass.Afterthe Unlock Bypass command issue Unlock Bypass Programor Unlock Bypass Reset commands.
Unlock Bypass Reset.Afterthe Unlock Bypass Resetcommandreadthe memory asnormaluntil another commandis issued.
Erase Suspend. Afterthe Erase Suspend command readnon-erasing memory blocksas normal, issueAuto Selectand Program commands non-erasing blocksas normal.
Erase Resume.Afterthe Erase Resume commandthe suspended Erase operation resumes,readthe Status Registeruntilthe Program/
Erase Controller completesandthe memory returnsto Read Mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset F0 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Unlock Bypass Reset Command. The Unlock
Bypass Reset command canbe usedto returnto
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operationsare requiredto issuethe
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase com-
mand canbe usedto erasethe entire chip.Six Bus
Write operations are requiredto issue the Chip
Erase Command and start the Program/Erase
Controller. any blocksare protected then theseare ignored
andallthe other blocks are erased.Ifallofthe
blocksare protectedthe Chip Erase operationap-
pears tostartbutwill terminate within about 100μs,
leavingthe data unchanged.No error conditionis
given when protected blocksare ignored.
Duringthe erase operationthe memorywill ignore
all commands.Itisnot possibleto issueany com-
mandto abortthe operation. Typical chip erase
timesare givenin Table6.All Bus Read opera-
tions duringthe Chip Erase operationwill output
the Status Registeronthe Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe Chip Erase operation has completedthe
memorywill returntothe Read Mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read Mode.
The Chip Erase Command setsallofthebitsinun-
protected blocksofthe memoryto’1’.All previous
datais lost.
M29F010B
8/20
Block Erase Command. The Block Erase com-
mand canbe usedto erasealistof oneor more
blocks.Six Bus Write operations are requiredto
select the first blockin the list. Each additional
blockinthelist canbe selectedby repeatingthe
sixth Bus Write operation usingthe addressofthe
additional block. The Block Erase operation starts
the Program/Erase Controller about 50μs afterthe
last Bus Write operation. Oncethe Program/Erase
Controller startsitis not possibleto select any
more blocks. Each additional block must therefore selected within 50μsofthelast block. The 50μs
timer restarts whenan additional blockis selected.
The Status Register canbe read after the sixth
Bus Write operation. Seethe Status Registerfor
detailson howto identifyif the Program/Erase
Controller has startedthe Block Erase operation. any selected blocksare protected then theseare
ignored andall the other selected blocks are
erased.Ifallofthe selected blocksare protected
the Block Erase operation appearsto startbutwill
terminate within about 100μs, leavingthe dataun-
changed.No error conditionis given when protect- blocksare ignored.
Duringthe Block Erase operationthe memorywill
ignoreall commands exceptthe Erase Suspend
and Read/Reset commands. Typical block erase
times are givenin Table6.All Bus Read opera-
tions duringthe Block Erase operationwill output
the Status Registeron the Data Inputs/Outputs.
Seethe sectiononthe Status Registerfor more
details.
Afterthe Block Erase operation has completedthe
memorywill returntothe Read Mode, unlessan
error has occurred. Whenan error occurs the
memorywill continueto outputthe Status Regis-
ter.A Read/Reset command mustbe issuedtore-
setthe error condition and returnto Read mode.
The Block Erase Command setsallofthe bitsin
the unprotected selected blocksto’1’.All previous
datainthe selected blocksis lost.
Erase Suspend Command. The Erase Suspend
Command maybe usedto temporarily suspenda
Block Erase operation and returnthe memoryto
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controllerwill suspend within
15μsof the Erase Suspend Command beingis-
sued. Once the Program/Erase Controller has
stoppedthe memorywillbesetto Read mode and
the Erasewillbe suspended.Ifthe Erase Suspend
commandis issued during the period whenthe
memoryis waitingforan additional block (before
the Program/Erase Controller starts) then the
Eraseis suspended immediately andwill startim-
mediately whenthe Erase Resume Commandis
issued.Itwillnotbe possibleto select any further
blocksfor erasure afterthe Erase Resume.
During Erase Suspenditis possibleto Read and
Program cellsin blocks thatarenot being erased;
both Read and Program operations behaveas
normalon these blocks. Reading from blocks that
are being erasedwill outputthe Status Register.It also possibleto enterthe Auto Select mode:the
memorywill behaveasinthe Auto Select modeon
all blocks untila Read/Reset command returnsthe
memoryto Erase Suspend mode.
Erase Resume Command. The Erase Resume
command mustbe usedto restartthe Program/
Erase Controller from Erase Suspend.An erase
canbe suspended and resumed more than once.
Table6. Program, Erase Times and Program, Erase Endurance Cycles
(TA=0to 70°C, –40to 85°Cor –40to 125°C)
Note:1.TA =25°C,VCC =5V.
Parameter Min Typ(1) Typical after
100k W/E Cycles(1) Max Unit
Chip Erase(Allbitsinthe memorysetto‘0’) 0.6 0.6 sec
Chip Erase 1.5 1.5 sec
Block Erase(16 Kbytes) 0.3 0.3 t.b.d. sec
Program 8 8 μs
Chip Program 1.2 1.2 sec
Program/Erase Cycles(per Block) 100,000 cycles
9/20
M29F010B
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.Itis also read during Erase Sus-
pend whenan address within ablock being erased accessed.
Thebitsinthe Status Registerare summarizedin
Table7, Status Register Bits.
Data PollingBit (DQ7). The Data PollingBit can usedto identify whether the Program/Erase
Controller has successfully completedits opera-
tionorifit has respondedtoan Erase Suspend.
The Data PollingBitis outputon DQ7 whenthe
Status Registeris read.
During Program operationsthe Data PollingBit
outputs the complementof thebit being pro-
grammedto DQ7. After successful completionof
the Program operation the memory returnsto
Read mode and Bus Read operationsfromthead-
dress just programmed output DQ7,notits com-
plement.
During Erase operationsthe Data PollingBit out-
puts’0’, the complementof the erased stateof
DQ7. After successful completionofthe Eraseop-
erationthe memory returnsto Read Mode. Erase Suspend modethe Data PollingBitwill
outputa’1’ duringa Bus Read operation withina
block being erased. The Data PollingBit will
change froma’0’toa’1’ whenthe Program/Erase
Controller has suspendedthe Erase operation.
Figure3, Data Polling Flowchart, givesan exam-
pleof howtousethe Data PollingBit.A ValidAd-
dressis the address being programmedoran
address withinthe block being erased.
ToggleBit (DQ6). The ToggleBit canbe usedto
identify whetherthe Program/Erase Controller has
successfully completedits operationorifithasre-
spondedtoan Erase Suspend. The ToggleBitis
outputon DQ6 whenthe Status Registeris read.
During Program and Erase operationsthe Toggle
Bit changes from’0’to’1’to’0’, etc., with succes-
sive Bus Read operationsat any address. After
successful completionofthe operationthe memo- returnsto Read mode.
During Erase Suspend modethe ToggleBitwill
output when addressingacell withina block being
erased. The ToggleBitwill stop toggling whenthe
Program/Erase Controller has suspended the
Erase operation.
Figure4, Data Toggle Flowchart, givesan exam-
pleof howto usethe Data ToggleBit.
ErrorBit (DQ5). The ErrorBit canbe usedto
identify errors detectedby the Program/Erase
Controller. The ErrorBitissetto’1’ whena Pro-
gram, Block Eraseor Chip Erase operation failsto
writethe correct datatothe memory.Ifthe Error
Bitisseta Read/Reset command mustbe issued
before other commandsare issued. The Errorbit outputon DQ5 whenthe Status Registeris read.
Note thatthe Program command cannot changea
bitsetat’0’ backto’1’ and attemptingtodosowill
causean error. Oneofthe Erase commands must usedtosetallthebitsina blockorinthe whole
memory from’0’to’1’.
Table7. Status Register Bits
Note: Unspecifieddatabits shouldbe ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2
Program Any Address DQ7 Toggle 0 – –
Program During Erase Suspend Any Address DQ7 Toggle 0 – –
Program Error Any Address DQ7 Toggle 1 – –
Chip Erase Any Address 0 Toggle 0 1 Toggle
Block Erase before timeout
Erasing Block 0 Toggle 0 0 Toggle
Non-Erasing Block 0 Toggle 0 0 No Toggle
Block Erase
Erasing Block 0 Toggle 0 1 Toggle
Non-Erasing Block 0 Toggle 0 1 No Toggle
Erase Suspend
Erasing Block 1 No Toggle 0 1 Toggle
Non-Erasing Block Data readas normal
Erase Error
Good Block Address 0 Toggle 1 1 No Toggle
Faulty Block Address 0 Toggle 1 1 Toggle
M29F010B
10/20
Figure3. Data Polling Flowchart
READDQ5& DQ7 VALID ADDRESS
START
READDQ7
FAIL PASS
AI01369
DQ7 =
DATA
YES
YES
DQ5
DQ7 = DATA
YES
Figure4. Data Toggle Flowchart
READ
DQ5 &DQ6
START
READDQ6
FAIL PASS
AI01370
DQ6 = TOGGLE
YES
YES
DQ5
YES
DQ6 = TOGGLE
Erase TimerBit (DQ3). The Erase TimerBit can usedto identify the startof Program/Erase
Controller operation duringa Block Erase com-
mand. Oncethe Program/Erase Controller starts
erasingthe Erase TimerBitissetto’1’. Beforethe
Program/Erase Controller startsthe Erase Timer
Bitissetto’0’ and additional blockstobe erased
maybe writtentothe Command Interface. The
Erase TimerBitis outputon DQ3 whenthe Status
Registeris read.
Alternative ToggleBit (DQ2). The Alternative
ToggleBit canbe usedto monitorthe Program/
Erase controller during Erase operations. TheAl-
ternative ToggleBitis outputon DQ2 whenthe
Status Registeris read.
During Chip Erase and Block Erase operationsthe
ToggleBit changes from’0’to’1’to’0’, etc., with
successive Bus Read operations from addresses
withinthe blocks being erased. Oncethe operation
completesthe memory returnsto Read mode.
During Erase Suspendthe Alternative ToggleBit
changes from’0’to’1’to’0’, etc. with successive
Bus Read operations from addresses withinthe
blocks being erased. Bus Read operationstoad-
dresses within blocksnot being erasedwill output
the memorycell dataasifin Read mode.
Afteran Erase operation that causesthe ErrorBitbesetthe Alternative ToggleBit canbe usedto
identify which blockor blocks have causedtheer-
ror. The Alternative ToggleBit changes from’0’to
’1’to’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that havenot
erased correctly. The Alternative ToggleBit does
not changeifthe addressed block has erased cor-
rectly.

Partno	Mfg	Dc	Qty	Available	Descript
29F010	AMD	N/a	4130	avai	1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only / Uniform Sector Flash Memory