28C16-M28C16-M28C16-150N6T-M28C16-150WK1TR-M28C16A Fast Delivery |IC PHOENIX CO.,LIMITED

28C16 ,16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTIONM28C1616K (2K x 8) PARALLEL EEPROMwith SOFTWARE DATA PROTECTIONNOT FOR NEW DESIGNFAST ACCESS TIME: ..
28C256 ,256K 32K x 8 Paged CMOS E2PROMAT28C256
28C64 , 64K (8K x 8) CMOS E2PROM with Page Write and Software Data Protection
28C64A-20P , 64K (8K x 8) CMOS EEPROM
28C64A-25P , 64K (8K x 8) CMOS EEPROM
28CPQ060 ,28Amp Dual Schottky Center Tap RectifiersFeatures I 28 Amp Continuous Output Current I Low Voltage Drop l Low Reverse Leakage " I ..
2SB1220 ,Small-signal deviceElectrical Characteristics T = 25°C ± 3°CaParameter Symbol Conditions Min Typ Max UnitCollector-em ..
2SB1220 ,Small-signal deviceAbsolute Maximum Ratings T = 25°CaParameter Symbol Rating Unit1: BaseCollector-base voltage (Emitt ..
2SB1223 ,PNP Epitaxial Planar Silicon Darlington Transistors Driver ApplicationsAbsolute Maximum Ratings at Ta = 25˚CPl arameter Ss ymbo Cs ondition Rt ating UniCV ollector-to-Bas ..
2SB1224 ,PNP Epitaxial Planar Silicon Darlington Transistors Driver ApplicationsAbsolute Maximum Ratings at Ta = 25˚CPl arameter Ss ymbo Cs ondition Rt ating UniCV ollector-to-Bas ..
2SB1225 ,PNP Epitaxial Planar Silicon Darlington Transistor Driver ApplicationsAbsolute Maximum Ratings at Ta = 25˚CPl arameter Ss ymbo Cs ondition Rt ating UniCV ollector-to-Bas ..
2SB1227 ,PNP Epitaxial Planar Silicon Darlington Transistors Driver ApplicationsAbsolute Maximum Ratings at Ta = 25˚CPl arameter Ss ymbo Cs ondition Rt ating UniCV ollector-to-Bas ..

28C16-M28C16-M28C16-150N6T-M28C16-150WK1TR-M28C16A
16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTION
M28C16
16K (2Kx 8)P ARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
November 1997 1/18
AI01518B
A0-A10
DQ0-DQ7
VCC
M28C16
VSS*
Figure1. Logic Diagram-A10 Address Input
DQ0- DQ7 Data Input/ Output Write Enable Chip Enable Output Enable Ready/ Busy
VCC Supply Voltage
VSS Ground
Table1. Signal Names
FAST ACCESS TIME: 90ns
SINGLE5V± 10%SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE:64 Bytes Page Write Operation Byteor Page Write Cycle: 3ms Max
ENHANCED ENDOF WRITE DETECTION: Data Polling ToggleBit
PAGE LOAD TIMER STATUSBIT
HIGH RELIABILITYSINGLE POLYSILICON,
CMOS TECHNOLOGY: Endurance >100,000 Erase/Write Cycles Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
M28C16is replacedbythe products
describedonthe document M28C16A
DESCRIPTION
The M28C16isa2Kx8 low power Parallel
EEPROM fabricatedwithSGS-THOMSON proprie-
tary single polysilicon CMOS technology.Thede-
vice offers fast access time with low power
dissipation and requiresa5V power supply. The
circuit has been designedto offera flexible micro-
controller interface featuring both hardware and
software handshakingwith DataPolling andToggle
Bit. The M28C16 supports64 byte page writeop-
eration.A Software Data Protection (SDP)is also
possible usingthe standard JEDEC algorithm.
PDIP24(P) PLCC32(K)
TSOP28(N) x13.4mm
SO24 (MS)
300mils
Note:*RB function isofferedonly withTSOP28 package.
DQ0
A10
DQ7
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6
VCC
AI01485
M28C16 13
Figure2A. DIPPin Connections
AI01486C
A10
DQ4
DQ0
DQ1DQ2
DQ3
DQ6
DQ7V
M28C16
DQ5
Figure2B. LCCPin Connections
Warning:NC=Not Connected,DU= Don’tUse
DQ0
DQ1
A10
DQ7
DQ5
VCC
DQ4A4
AI01519
M28C16
DQ2
VSS
DQ6
DQ3
Figure2C. SO Pin Connections
DQ0
DQ7
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6CC
AI01175C
M28C1628SS
A10
Figure2D. TSOPPin Connections
Warning:NC=Not Connected.
2/18
M28C16
Symbol Parameter Value Unit Ambient Operating Temperature –40to125 °C
TSTG Storage Temperature Range –65to150 °C
VCC Supply Voltage –0.3to6.5 V
VIO Input/Output Voltage –0.3toVCC +0.6 V Input Voltage –0.3to6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)(2) 4000 V
Notes:1. Exceptfor therating ”Operating Temperature Range”, stresses above those listedinthe Table ”Absolute MaximumRatings”may
cause permanent damagetothe device. Theseare stressratingsonlyand operationofthe deviceat theseorany other conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating
conditionsfor extended periods mayaffect devicereliability. Referalsoto theSGS-THOMSON SURE Programand other
relevant quality documents. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Table2. Absolute Maximum Ratings(1)
PIN DESCRIPTION
Addresses (A0-A10). The address inputs select 8-bit memory location duringa reador write
operation.
Chip Enable (E). The chip enable input mustbe
lowto enableall read/write operations.When Chip
Enableis high, power consumptionis reduced.
Output Enable (G). The Output Enable input con-
trolsthe data output buffersandis usedto initiate
read operations.
DataIn/ Out(DQ0- DQ7). Datais written toor read
fromthe M28C16throughtheI/O pins.
Write Enable (W). The Write Enable input controls
the writingof datatothe M28C16.
Ready/Busy (RB). Ready/Busyisan open drain
output that canbe usedto detectthe endofthe
internal write cycle.is offered only with theTSOP28 package. The
readershould referto theM28C17 datasheetfor
more information aboutthe Ready/Busy func-
tion.
OPERATION orderto prevent data corruption and inadvertent
write operationsan internal VCC comparator inhib-
its Write operationif VCCis belowVWI (see Table
7). Accesstothe memoryin write modeis allowed
aftera power-upas specifiedin Table7.
Read
The M28C16is accessedlikea staticRAM. When andGarelow withW high,the data addressed presentedontheI/O pins. TheI/O pinsare high
impedance when eitherGorEis high.
Write
Write operationsare initiated when bothW andE
arelow andGis high.The M28C16 supports both andW controlled write cycles. The Addressis
latchedbythe falling edgeofEorW which ever
occurslast andthe Dataonthe rising edgeofEor which ever occurs first. Once initiatedthe write
operationis internallytimed until completion.
Mode E G W DQ0- DQ7
Standby 1 X X Hi-Z
Output Disable X 1 X Hi-Z
Write Disable X X 1 Hi-Z
Read 0 0 1 DataOut
Write 0 1 0 DataIn
Chip Erase 0 V 0 Hi-Z
Note:1.0= VIL;1= VIH;X=VILorVIH;V=12±5%.
Table3. OperatingModes(1)
3/18
M28C16
Page Write
Page write allowsupto64 bytestobe consecu-
tively latched intothe memory priorto initiatinga
programming cycle.All bytes mustbe locatedina
single page address, thatis A6-A10 mustbethe
sameforall bytes. The page writecanbe initiated
during any byte write operation.
Followingthe first byte write instructionthe host
may send another address and data witha mini-
mum data transfer rateof 1/tWHWH (see Figure 13). atransitionof EorWisnot detectedwithin tWHWH,
the internal programming cyclewill start.
Chip Erase
The contentsofthe entire memory maybe erased FFhby useof the Chip Erase commandby
setting Chip Enable(E) Low and Output Enable
(G)to VCC +7V. The chipis cleared whena 10ms
low pulseis appliedtothe Write Enablepin.
Microcontroller Control Interface
The M28C16 provides two write operation status
bitsandone statuspinthat canbeusedto minimize
the system write cycle. Thesesignalsare availabletheI/O port bits DQ7or DQ6ofthe memory
during programmingcycle only.
Data Pollingbit (DQ7). Duringthe internal write
cycle,any attemptto readthelast byte writtenwill
produceon DQ7the complementary valueofthe
previously latchedbit. Oncethe write cycleisfin-
ishedthe true logic value appearson DQ7inthe
read cycle.
Togglebit (DQ6). The M28C16 offers another way
for determining when the internal write cycleis
completed. Duringthe internal Erase/Write cycle,
DQ6will toggle from”0”to”1” and”1”to”0” (the
first read valueis ”0”)on subsequent attemptsto
readthe memory. Whenthe internal cycleis com-
pletedthe togglingwill stop andthe devicewillbe
accessiblefora new Reador Write operation.
Page Load Timer Statusbit (DQ5).Inthe Page
Write mode data maybe latchedbyEorW.Upto bytes maybe input. The Data output (DQ5)
indicates the statusof the internal Page Load
Timer. DQ5 maybe readby asserting OutputEn-
able Low (tPLTS). DQ5 Low indicatesthe timeris
running, High indicates time-out after whichthe
writecyclewill start andno new data maybe input.
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Figure4. StatusBit Assignment =Data Polling= ToggleBit
PLTS= PageLoad Timer Status
AI01520
ADDRESS
LATCHA6-A10
(Page Address)
DECODE
CONTROL LOGIC
64KARRAY
ADDRESS
LATCHA0-A5 DECODE
VPPGEN RESET
SENSEAND DATA LATCH
I/O BUFFERS W
PAGE LOAD
TIMER STATUS
TOGGLEBIT
DATA POLLING
DQ0-DQ7
Figure3. Block Diagram
4/18
M28C16
Software Data Protection
The M28C16 offersa software controlled write
protection facility that allowsthe userto inhibitall
write modestothe device includingthe Chip Erase
instruction. This canbe usefulin protectingthe
memory from inadvertent write cycles that may
occurdueto uncontrolledbus conditions.
The M28C16is shipped asstandardinthe ”unpro-
tected” state meaning thatthe memory contents
canbe changedas requiredbythe user. Afterthe
Software Data Protection enable algorithmisis-
sued, the device enters the ”Protect Mode”of
operation whereno further write commands have
any effecton the memory contents. The device
remainsin this mode untila valid Software Data
Protection (SDP) disable sequenceis received
whereby the device revertstoits ”unprotected”
state. The Software Data Protectionis fully non-
volatile andisnot changedby power on/offse-
quences. enablethe SoftwareData Protection(SDP)the
device requiresthe userto write (witha Page Write)
three specific data bytesto three specific memory
locationsasper Figure5. Similarlyto disablethe
Software Data Protection the user hasto write
specificdatabytesintosix differentlocations asper
Figure6 (witha Page Write). This complex series
ensures thatthe userwill never enableor disable
the Software Data Protectionaccidentally.
AI01509B
WRITEAAhin
Address 555h
WRITE55hin
Address 2AAh
WRITEA0hin
Address 555h
SDPisset
WRITEAAhin
Address555h
WRITE55hin
Address 2AAh
WRITEA0hin
Address555h
Write Page up to64 bytes)
WRITEIN MEMORY
WHENSDPISSET
SDP ENABLE ALGORITHM
Page
Write
Instruction
(Note1)
Page
Write
Instruction
(Note1)
WRITE enabled
Figure5. Software DataProtection Enable Algorithm and Memory Write
AI01510
WRITEAAhin
Address 555h
WRITE55hin
Address 2AAh
WRITE80hin
Address 555h
Unprotected State
WRITEAAhin
Address 555h
WRITE55hin
Address 2AAh
WRITE20hin
Address 555h
Page
Write
Instruction
Figure6. Software DataProtection Disable
Algorithm
Note:1. MSB Addressbits (A6toA10) differduring these specific Page Write operations.
5/18
M28C16
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:1. Sampledonly, not100% tested.
Table5. Capacitance(1) (TA =25°C,f=1 MHz)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤VIN≤VCC 10 μA
ILO Output Leakage Current 0V≤VIN≤VCC 10 μA
ICC(1) Supply Current (TTL inputs) E= VIL,G=VIL,f=5 MHz 30 mA
Supply Current (CMOS inputs) E= VIL,G=VIL,f=5 MHz 25 mA
ICC1(1) Supply Current (Standby)TTL E=VIH 1mA
ICC2(1) Supply Current (Standby) CMOS E>VCC –0.3V 100 μA
VIL InputLow Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC +0.5 V
VOL OutputLow Voltage IOL=2.1mA 0.4 V
VOH Output High Voltage IOH= –400μA 2.4 V
Note:1.AllI/O’sopen circuit.
Table6. Read ModeDC Characteristics (TA=0to 70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
Symbol Parameter Min Max Unit
tPUR Time Delayto Read Operation 1 μs
tPUW Time Delayto Write Operation (onceVCC ≥ 4.5V) 10 ms
VWI Write Inhibit Threshold 3.0 4.2 V
Note:1. Sampledonly, not100% tested.
Table7. PowerUp Timing(1) (TA=0to 70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
Input RiseandFall Times ≤ 20ns
Input Pulse Voltages 0.4Vto 2.4V
Inputand Output TimingRef. Voltages 0.8Vto 2.0V
Notethat OutputHi-Z isdefinedasthepoint wheredataisno
longer driven.
Table4. AC Measurement Conditions
AI00826
2.4V
0.4V
2.0V
0.8V
Figure7.AC Testing Input Output Waveforms
AI01129
1.3V
OUTL= 30pF includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure8. AC Testing Equivalent Load Circuit
6/18
M28C16
Symbol Alt Parameter Test
Condition
M28C16
Unit-90 -120 -150
min max min max min max
tAVQV tACC Address Validto
Output ValidVIL,VIL 90 120 150 ns
tELQV tCE Chip EnableLowto
Output Valid G=VIL 90 120 150 ns
tGLQV tOE Output EnableLow Output Valid E=VIL 40 45 50 ns
tEHQZ(1) tDF Chip Enable High Output Hi-Z G=VIL 040 0 45 050 ns
tGHQZ(1) tDF Output Enable High Output Hi-Z E=VIL 040 0 45 050 ns
tAXQX tOH Address Transition Output TransitionVIL,VIL 00 0 ns
Note: 1.OutputHi-Zis definedasthepointat whichdatais nolonger driven.
Table8. Read ModeAC Characteristics
(TA=0 to70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
AI01511B
VALID
tAVQV tAXQX
tGLQV tEHQZ
tGHQZ
DATAOUT
A0-A10
DQ0-DQ7
tELQV
Hi-Z
Figure9. Read ModeAC Waveforms
Note: WriteEnable(W)=High
7/18
M28C16
Symbol Alt Parameter TestCondition Min Max Unit
tAVWL tAS Address Validto Write EnableLow E= VIL,G=VIH 0ns
tAVEL tAS Address Validto Chip Enable Low G= VIH,W=VIL 0ns
tELWL tCES Chip EnableLowto Write EnableLow G=VIH 0ns
tGHWL tOES Output Enable Highto Write Enable
Low E=VIL 0ns
tGHEL tOES Output Enable Highto Chip EnableLow W=VIL 0ns
tWLEL tWES Write EnableLowto Chip EnableLow G=VIH 0ns
tWLAX tAH Write EnableLowto Address Transition 50 ns
tELAX tAH Chip EnableLow toAddress Transition 50 ns
tWLDV tDV Write EnableLowto Input Valid E= VIL,G=VIH 1 μs
tELDV tDV Chip EnableLowto Input Valid G= VIH,W=VIL 1 μs
tELEH tWP Chip EnableLowto Chip Enable High 50 ns
tWHEH tCEH Write Enable Highto Chip Enable High 0 ns
tWHGL tOEH Write Enable Highto Output Enable
Low 0ns
tEHGL tOEH Chip Enable Highto Output EnableLow 0 ns
tEHWH tWEH Chip Enable Highto Write Enable High 0 ns
tWHDX tDH Write Enable Highto Input Transition 0 ns
tEHDX tDH Chip Enable Highto Input Transition 0 ns
tWHWL tWPH Write Enable Highto Write EnableLow 50 ns
tWLWH1 tWP Write EnableLowto Write EnableHigh 50 ns
tWHWH tBLC Byte Load Repeat Cycle Time 0.15 100 μs
tWHRH tWC Write Cycle Time 3 ms
tDVWH tDS Data Valid before Write Enable High 50 ns
tDVEH tDS Data Valid before Chip Enable High 50 ns
Table9. Write ModeAC Characteristics
(TA=0 to70°Cor –40to 85°C; VCC= 4.5Vto 5.5V)
8/18
M28C16
AI01207
VALID
tAVWL
A0-A10
DQ0-DQ7 DATAIN
tWLAX
tELWL
tGHWL
tWLDV
tWHEH
tWHGLtWLWH1
tWHWL
tWHDXtDVWH
Figure10. Write ModeAC Waveforms- Write Enable Controlled
AI01522
VALID
tAVEL
A0-A10
DQ0-DQ7 DATAIN
tELAX
tGHEL
tWLEL
tELDV
tEHGL
tEHDXtDVEH
tELEH
tEHWH
Figure11. Write ModeAC Waveforms- Chip Enable Controlled
9/18
M28C16

Partno	Mfg	Dc	Qty	Available	Descript
M28C16	OKI	N/a	830	avai	16K (2K X 8) PARALLEL EEPROM WITH SOFTWARE DATA PROTECTION
M28C16-150N6T \|M28C16150N6T	STM	N/a	1000	avai	16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTION
M28C16-150WK1TR \|M28C16150WK1TR	ST	N/a	2250	avai	16 Kbit 2K x 8 Parallel EEPROM With Software Data Protection
M28C16A	OKI	N/a	6100	avai	16 Kbit (2Kb x8) Parallel EEPROM
28C16	ATM	N/a	8000	avai	16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTION