27C4002 Fast Delivery |IC PHOENIX CO.,LIMITED

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27C4002
4 Mbit 256Kb x16 UV EPROM and OTP EPROM
M27C4002 Mbit (256Kb x16) UV EPROM and OTP EPROM
September 1998 1/16
AI00727B
A0-A17 Q0-Q15
VPPVCC
M27C4002
VSS
Figure1. Logic Diagram± 10% SUPPLY VOLTAGEin READ
OPERATION
FASTACCESS TIME: 45ns
LOW POWER CONSUMPTION: Active Current 70mAat 10MHz Standby Current 100μA
PROGRAMMING VOLTAGE: 12.75V± 0.25V
PROGRAMMING TIME: 100μs/byte (typical)
ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 0044h
DESCRIPTION
The M27C4002isa4 Mbit EPROM offeredinthe
two rangesUV (ultra violet erase) and OTP (one
time programmable).Itis ideally suitedfor micro-
processorsystemsrequiring large programsandis
organisedas 262,144wordsof16 bits.
The FDIP40W (window ceramic frit-seal package)
andthe JLCC44W (J-lead chip carrier packages)
have transparentlids which allowthe usertoex-
pose the chipto ultraviolet lightto erasethebit
pattern.A new pattern can thenbe writtentothe
deviceby followingthe programming procedure.
Forapplications wherethe contentis programmed
only one time and erasureis not required, the
M27C4002is offeredin PDIP40, PLCC44 and
TSOP40(10x20 mm) packages.
A0-A17 Address Inputs
Q0-Q15 Data Outputs Chip Enable Output Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
Table1. SignalNames
FDIP40W(F)
TSOP40(N)x20mm
PLCC44(C)
PDIP40(B)
JLCC44W(J)
Q11
VSS
Q10
A12
A11
A10
A13
VSSQ1G
A16
A17E
Q12PP VCC
Q15
AI00728
M27C400220
Q14
Q13
A14
A15
Figure2A. DIPPin Connections
AI00729
A14
A11Q2
Q12
VSS
Q11
Q10
A15
Q15
VSS
A12
Q13 A16
M27C4002
Q14
A13 A10Q7A1 A17V
Figure2B. LCCPin Connections
Warning:NC=Not Connected.
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A11
A10
A15
DQ1
DQ0
A16
A17
DQ14
VPP
VCC
DQ15
AI01831
M27C4002
(Normal) 21
VSS
A12 A6
A13 A5
DQ12 DQ4
DQ11 DQ5
VSS
Figure2C. TSOPPin Connections DEVICE OPERATION
The operating modesofthe M27C4002are listedthe Operating Modes table.A single power sup-
plyis requiredinthe read mode.All inputsare TTL
levels exceptforVpp and 12VonA9for Electronic
Signature.
Read Mode
The M27C4002 has two control functions, bothof
which mustbe logically activein orderto obtain
dataatthe outputs. Chip Enable(E)isthe power
control and shouldbe usedfor device selection.
OutputEnable(G)isthe output control and should usedto gate datato the output pins, inde-
pendentof device selection. Assuming thatthe
addressesare stable,the address access time
(tAVQV)isequaltothe delayfrom Etooutput (tELQV).
Datais availableat theoutput aftera delayof tGLQV
fromthe falling edgeofG, assuming thatE has
beenlow andthe addresses have been stablefor least tAVQV-tGLQV.
Standby Mode
The M27C4002 hasa standby mode whichre-
ducesthe supplycurrentfrom 50mAto 100μA. The
M27C4002is placedinthe standby modebyap-
plyinga CMOShigh signalto theE input. Whenin
the standby mode, theoutputsareina high imped-
ance state, independentoftheG input.
2/16
M27C4002
Two Line Output Control
BecauseEPROMsare usuallyusedin larger mem-
ory arrays,the product featuresa2 line control
function which accommodatesthe useof multiple
memory connection. The twoline control function
allows:the lowest possible memory power dissipation, complete assurance that output bus contention
willnot occur.
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40 to125 °C
TBIAS Temperature Under Bias –50 to125 °C
TSTG Storage Temperature –65 to150 °C
VIO(2) Inputor Output Voltages (exceptA9) –2to7 V
VCC Supply Voltage –2to7 V
VA9(2) A9 Voltage –2 to13.5 V
VPP Program Supply Voltage –2 to14 V
Notes:1. Exceptfor therating ”OperatingTemperature Range”, stresses above those listedin theTable ”Absolute Maximum Ratings”
may cause permanentdamageto thedevice. Theseare stress ratingsonlyand operationofthe deviceat theseorany other
conditions above those indicatedinthe Operatingsectionsofthis specificationis notimplied. Exposureto Absolute Maximum
Rating conditionsfor extendedperiodsmay affectdevice reliability.Referalsotothe STMicroelectronics SURE Programand other
relevant qualitydocuments. MinimumDC voltageonInputor Outputis –0.5Vwith possibleundershootto –2.0Vfor aperiodlessthan 20ns. MaximumDC
voltageon OutputisVCC +0.5Vwith possible overshoottoVCC+2Vfora periodlessthan 20ns. Dependson range.
Table2. Absolute MaximumRatings(1)
Mode E G A9 VPP Q0- Q15
Read VIL VIL XVCCorVSS DataOut
Output Disable VIL VIH XVCCorVSS Hi-Z
Program VIL Pulse VIH XVPP DataIn
Verify VIH VIL XVPP DataOut
Program Inhibit VIH VIH XVPP Hi-Z
Standby VIH XX VCCorVSS Hi-Z
Electronic Signature VIL VIL VID VCC Codes
Note:X=VIHor VIL,VID=12V±0.5V
Table3. Operating Modes
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code VIL 001 0000 0 20h
Device Code VIH 010 0010 0 44h
Note: Outputs Q8-Q15aresetto’0’.
Table4. Electronic Signature
Forthe mostefficientuseof thesetwo controllines, shouldbe decoded and usedasthe primary
device selecting function, whileG shouldbe made common connectiontoall devicesin the array
and connectedtothe READline fromthe system
control bus. This ensures thatall deselectedmem-
ory devicesarein their low power standby mode
and thatthe output pinsare only active when data required froma particular memory device.
3/16
M27C4002
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:1. Sampled only,not 100% tested.
Table6. Capacitance(1) (TA =25°C,f=1 MHz)
AI01822
High Speed
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure3.AC TestingInput Output Waveform
AI01823B
1.3V
OUT= 30pF forHigh Speed= 100pFfor Standard includes JIGcapacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure4.AC Testing Load Circuit
High Speed Standard
Input RiseandFall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0to3V 0.4Vto 2.4V
Inputand Output TimingRef. Voltages 1.5V 0.8Vand2V
Table5. AC Measurement Conditions
System Considerations
The power switching characteristicsof Advanced
CMOS EPROMs require careful decouplingofthe
devices. The supply current, ICC, has three seg-
ments thatareof interesttothe system designer:
the standby current level,the active current level,
and transient current peaks thatare producedby
thefalling and rising edgesofE. The magnitudeof
the transient current peaksis dependentonthe
output capacitive and inductive loadingofthede-
vice.
The associated transient voltage peaks canbe
suppressedby complying withthe twoline output
control andby properly selected decouplingca-
pacitors.Itis recommended thata 0.1μF ceramic
capacitorbe usedon every device between VCC
and VSS. Thisshouldbea highfrequencycapacitorlow inherent inductance and shouldbe placed closetothe deviceas possible.In addition,a
4.7μF bulk electrolytic capacitor shouldbe used
betweenVCC andVSSfor everyeightdevices. The
bulk capacitor shouldbe located nearthe power
supply connection point.The purposeof the bulk
capacitoristo overcomethe voltage drop causedthe inductive effectsof PCBtraces.
4/16
M27C4002
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤VIN≤VCC ±10 μA
ILO Output Leakage Current 0V≤ VOUT≤VCC ±10 μA
ICC Supply Current
E=VIL,G=VIL,
IOUT= 0mA,f= 10MHz 70 mA
E=VIL,G=VIL,
IOUT= 0mA,f= 5MHz 50 mA
ICC1 Supply Current (Standby)TTL E=VIH 1mA
ICC2 Supply Current (Standby) CMOS E>VCC– 0.2V 100 μA
IPP Program Current VPP =VCC 10 μA
VIL Input Low Voltage –0.3 0.8 V
VIH(2) Input High Voltage 2 VCC+1 V
VOL OutputLow Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –400μA 2.4 V
Output High VoltageCMOS IOH= –100μAVCC– 0.7V V
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. MaximumDC voltageon OutputisVCC +0.5V.
Table7. Read ModeDC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V±5%or5V± 10%;VPP =VCC)
Symbol Alt Parameter Test
Condition
M27C4002
Unit-45(3) -60(3) -80 -90
Min Max Min Max Min Max Min Max
tAVQV tACC Address Validto
Output ValidVIL,VIL 45 60 80 90 ns
tELQV tCE ChipEnable Low Output Valid G=VIL 45 60 80 90 ns
tGLQV tOE Output Enable
Lowto Output Valid E=VIL 25 30 40 40 ns
tEHQZ(2) tDF ChipEnable High Output Hi-Z G=VIL 0 30 0 30 0 30 0 30 ns
tGHQZ(2) tDF Output Enable
Highto Output Hi-Z E=VIL 0 30 0 30 0 30 0 30 ns
tAXQX tOH Address Transition Output TransitionVIL,VIL 0000 ns
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampled only,not 100% tested.Incaseof70ns speedseeHigh Speed ACMeasurement conditions.
Table8A. Read ModeAC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V±5%or5V± 10%;VPP =VCC)
5/16
M27C4002
AI00731B
tAXQX
tEHQZ
A0-A17
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Figure5. Read ModeAC Waveforms
Symbol Alt Parameter Test
Condition
M27C4002
Unit
-10 -12 -15 -20
Min Max Min Max Min Max Min Max
tAVQV tACC Address Validto
Output ValidVIL,VIL 100 120 150 200 ns
tELQV tCE Chip EnableLow
toOutput Valid G=VIL 100 120 150 200 ns
tGLQV tOE
Output Enable
Lowto Output
Valid
E=VIL 50 60 60 70 ns
tEHQZ(2) tDF Chip Enable High
toOutput Hi-Z G=VIL 0 30 0 40 0 50 0 80 ns
tGHQZ(2) tDF
Output Enable
Highto Output
Hi-Z
E=VIL 0 30 0 40 0 50 0 80 ns
tAXQX tOH
Address
Transitionto
Output TransitionVIL,VIL 00 00 ns
Table8B. ReadModeAC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V±5%or5V± 10%;VPP =VCC)
Programming
When delivered (and after each erasureforUV
EPROM),all bitsofthe M27C4002areinthe’1’
state. Datais introducedby selectively program-
ming ’0’s intothe desiredbit locations. Although
only’0’swillbe programmed,both’1’s and’0’scan presentin the data word. The only wayto
changea’0’toa’1’isbydie exposureto ultraviolet
light (UV EPROM). The M27C4002isinthe pro-
gramming mode whenVPP inputisat 12.75V,Gis VIH andEis pulsedto VIL. The datatobe
programmedis appliedto16 bitsin paralleltothe
data output pins. The levels requiredforthead-
dress and data inputsare TTL. VCCis specifiedto 6.25V± 0.25V.
6/16
M27C4002
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0≤VIN≤VCC ±10 μA
ICC Supply Current 50 mA
IPP Program Current E=VIL 50 mA
VIL InputLow Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC+0.5 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –400μA 2.4 V
VID A9 Voltage 11.5 12.5 V
Note:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP.
Table9. ProgrammingModeDC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V;VPP= 12.75V± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Validto Chip EnableLow 2 μs
tQVEL tDS Input Validto Chip EnableLow 2 μs
tVPHEL tVPS VPP Highto Chip EnableLow 2 μs
tVCHEL tVCS VCC Highto Chip EnableLow 2 μs
tELEH tPW Chip Enable Program Pulse
Width 95 105 μs
tEHQX tDH Chip Enable Highto Input
Transition 2 μs
tQXGL tOES Input Transitionto Output Enable
Low 2 μs
tGLQV tOE Output EnableLowto Output
Valid 100 ns
tGHQZ tDFP Output EnableHighto Output
Hi-Z 0 130 ns
tGHAX tAH Output EnableHighto Address
Transition 0ns
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampled only,not 100% tested.
Table10. ProgrammingModeAC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V;VPP= 12.75V± 0.25V)
7/16
M27C4002
tAVEL
VALID
AI00730
A0-A17
Q0-Q15
VPP
VCC
DATAIN DATAOUT
tQVEL
tVPHEL
tVCHEL
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM VERIFY
Figure6. Programmingand Verify ModesAC Waveforms
AI00726C0
Last
Addr
VERIFY= 100μs Pulse
++n
=25 ++Addr
VCC= 6.25V,VPP= 12.75V
FAIL
CHECKALL WORDS
1st:VCC =6V
2nd:VCC=4.2V
YES
YES
YES
Figure7. ProgrammingFlowchart PRESTOII ProgrammingAlgorithm
PRESTOII Programming Algorithm allows the
whole arraytobe programmed witha guaranteed
margin,ina typical timeof 26.5seconds.Program-
ming with PRESTOII consistsof applyingase-
quenceof 100μs programpulsesto each byte until correct verify occurs (see Figure7). During pro-
gramming and verify operation,a MARGIN MODE
circuitis automaticallyactivatedin orderto guaran-
tee that each cellis programmed with enough
margin.No overprogrampulseisapplied sincethe
verifyin MARGIN MODE provides necessarymar-
ginto each programmedcell.
Program Inhibit
Programmingof multiple M27C4002sin parallel
with different datais also easily accomplished.
ExceptforE,all like inputs includingGof the
parallel M27C4002 maybe common.A TTLlow
level pulse appliedtoa M27C4002’sE input, with
VPPat 12.75V,willprogramthat M27C4002. Ahigh
levelE input inhibitsthe other M27C4002s from
being programmed.
Program Verify verify (read) shouldbe performedonthe pro-
grammedbitsto determinethat theywere correctly
programmed. The verifyis accomplished withGat
VIL,Eat VIH, VPPat 12.75Vand VCCat 6.25V.
8/16
M27C4002

Partno	Mfg	Dc	Qty	Available	Descript
27C4002	ST	N/a	3000	avai	4 Mbit 256Kb x16 UV EPROM and OTP EPROM