27C160 Fast Delivery |IC PHOENIX CO.,LIMITED

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27C160
16 Mbit 2Mb x8 or 1Mb x16 UV EPROM and OTP EPROM
1/16February 1999
M27C160 Mbit (2Mb x8 or 1Mb x16) UV EPROM and OTP EPROM 5V± 10% SUPPLY VOLTAGEin READ
OPERATION FAST ACCESS TIME: 70ns BYTE-WIDEor WORD-WIDE
CONFIGURABLE 16 Mbit MASK ROM REPLACEMENT LOW POWER CONSUMPTION Active Current 70mAat 8MHz Standby Current 100μA PROGRAMMING VOLTAGE: 12.5V± 0.25V PROGRAMMING TIME: 100μs/byte (typical) ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 00B1h
DESCRIPTION
The M27C160isa16 Mbit EPROM offeredinthe
two rangesUV (ultra violet erase) and OTP (one
time programmable).Itis ideally suitedfor micro-
processor systemsrequiring large dataor program
storage andis organisedas either2 Mbit wordsofbitor1 Mbit wordsof16bit. The pin-outis com-
patible witha16 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
hasa transparentlid which allowsthe usertoex-
posethe chipto ultraviolet lightto erasethebit pat-
tern.
FDIP42W(F)
SO44(M)
PDIP42(B)
PLCC44(K)
Figure1. Logic Diagram
AI00739B
A0-A19
BYTEVPP
Q0-Q14
VCC
M27C160
VSS
Q15A–1
Table1. Signal Names
A0-A19 Address Inputs
Q0-Q7 Data Outputs
Q8-Q14 Data Outputs
Q15A–1 Data Output/ Address Input Chip Enable Output Enable
BYTEVPP Byte Mode/ Program Supply
VCC Supply Voltage
VSS Ground
M27C160
2/16
Figure2B. PLCC Pin Connections
Warning:NC=Not Connected.
AI03012
A11
A14Q2 NC
Q12
VSS
A10
A16
BYTEVPP
A13
M27C160
A12
Q13
VSS
Q14
Q10 A15
Q15A–1G
Q11Q4
A18A17 A8A19
Figure2A. DIPPin Connections
VSS
A13
VSS
A14
A15
A12
A16
BYTEVPP
Q15A-1Q2
VCCQ11
Q14A17
A18 A19
AI00740
M27C160
Q13
A11
A10
Q10
Q12 new patterncan thenbe written rapidlytothede-
viceby followingthe programming procedure.
For applications wherethe contentis programmed
only one time and erasureis not required, the
M27C160is offeredin PDIP42, PLCC44 and
SO44 packages.
DEVICE OPERATION
The operating modesofthe M27C160are listedin
the Operating Modes Table.A single power supply requiredinthe read mode.All inputsare TTL
compatible exceptfor VPP and 12VonA9forthe
Electronic Signature.
Read Mode
The M27C160 has two organisations, Word-wide
and Byte-wide. The organisationis selected bythe
signal levelonthe BYTEVPP pin. When BYTEVPPat VIHthe Word-wide organisationis selected
andthe Q15A–1pinis usedfor Q15 Data Output.
Whenthe BYTEVPPpinisatVILthe Byte-wideor-
ganisationis selected and theQ15A–1pin isused
forthe Address Input A–1. Whenthe memoryis
logically regardedas16bit wide,but readinthe
Byte-wide organisation, then with A–1atVIL the
lower8bitsofthe 16bit dataare selected and with
A–1atVIHthe upper8 bitsofthe16bit dataare
selected.
Figure2C.SOPin Connections
VSS
A13
VSS
A14
A15
A12
A16
BYTEVPP
Q15A-1Q2
VCCQ11
Q14
A19A18 NC
AI01264
M27C16022Q1
Q13
A11
A10
Q10
Q12
A17 A8
3/16
M27C160
The M27C160 has two control functions, bothof
which mustbe logically activein orderto obtain
dataatthe outputs.In additionthe Word-wideor
Byte- wide organisation mustbe selected.
Chip Enable(E)isthe power control and shouldbe
usedfor device selection. Output Enable(G)isthe
output control and shouldbe usedto gate datato
the output pins independentof device selection.
Assuming thatthe addressesare stable,thead-
dress access time (tAVQV)is equaltothe delay
fromEto output (tELQV). Datais availableatthe
output aftera delayof tGLQV fromthe falling edgeG, assuming thatE has been low andthead-
dresses have been stableforat least tAVQV-tGLQV.
Table2. Absolute Maximum Ratings(1)
Note:1. Exceptforthe rating ”Operating Temperature Range”, stressesabove those listedinthe Table ”Absolute Maximum Ratings”may
cause permanent damagetothe device. Theseare stress ratingsonlyand operationofthe device attheseor anyother conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periodsmay affect device reliability. Referalsotothe STMicroelectronics SUREProgram andotherrelevantqual-
ity documents. MinimumDC voltageon Inputor Outputis –0.5Vwith possible undershootto –2.0Vfora periodlessthan 20ns. MaximumDC
voltageon OutputisVCC +0.5Vwith possible overshoottoVCC+2Vfora periodless than20ns. Dependson range.
Table3. Operating Modes
Note:X=VIHor VIL,VID=12V± 0.5V.
Table4. Electronic Signature
Note: Outputs Q8-Q15aresetto’0’.
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40to125 °C
TBIAS Temperature Under Bias –50to125 °C
TSTG Storage Temperature –65to150 °C
VIO(2) Inputor Output Voltage (exceptA9) –2to7 V
VCC Supply Voltage –2to7 V
VA9(2) A9 Voltage –2to 13.5 V
VPP Program Supply Voltage –2to14 V
Mode E G BYTEVPP A9 Q0-Q7 Q8-Q14 Q15A–1
Read Word-wide VIL VIL VIH X DataOut DataOut DataOut
Read Byte-wide Upper VIL VIL VIL X DataOut Hi-Z VIH
Read Byte-wide Lower VIL VIL VIL X DataOut Hi-Z VIL
Output Disable VIL VIH X X Hi-Z Hi-Z Hi-Z
Program VIL Pulse VIH VPP X DataIn DataIn DataIn
Verify VIH VIL VPP X DataOut DataOut DataOut
Program Inhibit VIH VIH VPP X Hi-Z Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z Hi-Z
Electronic Signature VIL VIL VIH VID Codes Codes Code
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’sCode VIL 001 000 00 20h
Device Code VIH 101 100 01 B1h
M27C160
4/16
Standby Mode
The M27C160hasa standby mode which reduces
the active current from 50mAto 100μA. The
M27C160is placedinthe standby modeby apply-
inga CMOS high signaltothe Einput. Wheninthe
standby mode, the outputsareina high imped-
ance state, independentoftheG input.
Two Line Output Control
Because EPROMs are usually usedin larger
memory arrays,this product featuresa2line con-
trol function which accommodatesthe useof mul-
tiple memory connection. The two line control
function allows:the lowest possible memory power dissipation, complete assurance that output bus contention
willnot occur.
For the most efficient useof these two control
lines,E shouldbe decoded and usedasthe prima- device selecting function, whileG shouldbe
madea common connectiontoall devicesinthe
array and connectedto the READ line fromthe
system control bus. This ensures thatall deselect- memory devicesarein their lowpower standby
mode and that the output pins are only active
when datais required froma particular memory
device.
Table5.AC Measurement Conditions
High Speed Standard
Input RiseandFall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0to3V 0.4Vto 2.4V
Inputand Output Timing Ref. Voltages 1.5V 0.8Vand2V
Figure3. Testing Input Output Waveform
AI01822
High Speed
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure4.AC Testing Load Circuit
AI01823B
1.3V
OUT= 30pFfor HighSpeed= 100pFfor Standard includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table6. Capacitance(1)(TA =25°C,f=1 MHz)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN
Input Capacitance (except BYTEVPP)VIN =0V 10 pF
Input Capacitance (BYTEVPP)VIN=0V 120 pF
COUT Output Capacitance VOUT =0V 12 pF
5/16
M27C160
Table7. Read ModeDC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V±5%or5V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. MaximumDC voltageon OutputisVCC +0.5V.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤VIN≤ VCC ±1 μA
ILO Output Leakage Current 0V≤ VOUT≤VCC ±10 μA
ICC Supply Current VIL,G=VIL,
IOUT= 0mA,f= 8MHz 70 mA VIL,G=VIL,
IOUT= 0mA,f= 5MHz 50 mA
ICC1 Supply Current (Standby)TTL E=VIH 1mA
ICC2 Supply Current (Standby) CMOS E>VCC– 0.2V 100 μA
IPP Program Current VPP =VCC 10 μA
VIL InputLow Voltage –0.3 0.8 V
VIH(2) Input High Voltage 2 VCC+1 V
VOL OutputLow Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –400μA 2.4 V
System Considerations
The power switching characteristicsof Advanced
CMOS EPROMs require carefull decoupliingof
the suppliestothe devices. The supply currentICC
has three segmentsof importancetothe system
designer:the standby current,the active current
andthe transient peaks thatare producedbythe
falling and rising edgesofE.
The magnitudeofthe transient current peaksis
dependantonthe capacititive and inductive load-
ingofthe device outputs. The associated transient
voltage peaks canbe supressedby complying
withthetwoline output control andby properlyse-
lected decoupling capacitors.Itis recommended
thata 0.1μF ceramic capacitoris usedon every
device between VCC and VSS. This shouldbea
high frequency typeof low inherent inductance
and shouldbe placedas closeas possibletothe
device.In addition,a 4.7μF electrolytic capacitor
shouldbe used between VCC and VSSfor every
eight devices.
This capacitor shouldbe mounted nearthe power
supply connection point. The purposeof this ca-
pacitoristo overcomethe voltage drop causedby
the inductive effectsof PCB traces.
Programming
When delivered (and after each erasureforUV
EPROM),all bitsofthe M27C160 areinthe’1’
state. Datais introducedby selectively program-
ming ’0’s intothe desiredbit locations. Although
only’0’swillbe programmed, both’1’s and’0’s can presentin the data word. The only wayto
changea’0’toa’1’isbydie expositionto ultravio-
let light (UV EPROM). The M27C160isinthe pro-
gramming mode when VPP inputisat 12.5V,GisVIH andEis pulsedto VIL. The datatobe pro-
grammedis appliedto16bitsin paralleltothe data
output pins. The levels requiredfor the address
and data inputsare TTL. VCCis specifiedtobe
6.25V± 0.25V.
M27C160
6/16
Figure5. Word-Wide Read ModeAC Waveforms
Note: BYTEVPP =VIH.
AI00741B
tAXQX
tEHQZ
A0-A19
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Table8. Read ModeAC Characteristics(1)
(TA=0to70°Cor –40to85°C; VCC =5V±5%or5V± 10%; VPP =VCC)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP Sampledonly,not 100% tested. Speed obtainedwithHigh Speed Measurement Conditionsand VCC=5V±5%.
Symbol Alt Parameter Test Condition
M27C160
Unit-70(3) -90 -100 -120/-150
Min Max Min Max Min Max Min Max
tAVQV tACC Address Validto
Output Valid E=VIL,G=VIL 70 90 100 120 ns
tBHQV tST BYTE Highto
Output Valid E=VIL,G=VIL 70 90 100 120 ns
tELQV tCE Chip EnableLowto
Output Valid G=VIL 70 90 100 120 ns
tGLQV tOE Output EnableLow Output Valid E=VIL 35 45 50 60 ns
tBLQZ(2) tSTD BYTELowto Output
Hi-Z E=VIL,G=VIL 30 30 40 50 ns
tEHQZ(2) tDF Chip Enable Highto
OutputHi-Z G=VIL 0 25 0 30 0 40 0 50 ns
tGHQZ(2) tDF Output Enable High OutputHi-Z E=VIL 0 25 0 30 0 40 0 50 ns
tAXQX tOH Address Transition Output Transition E=VIL,G=VIL 55 55 ns
tBLQX tOH BYTELowto
Output Transition E=VIL,G=VIL 55 55 ns
7/16
M27C160
Figure6. Byte-Wide Read ModeAC Waveforms
Note: BYTEVPP =VIL.
Figure7. BYTE TransitionAC Waveforms
Note: Chip Enable(E)and Output Enable(G)=VIL.
AI00742B
tAXQX
tEHQZ
A–1,A0-A19
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
AI00743C
tAXQX
tBHQV
A0-A19
BYTEVPP
tAVQV
tBLQX
tBLQZ
VALID
Hi-Z
A–1
DATAOUT
DATAOUT
VALID
Q0-Q7
Q8-Q15
M27C160
8/16
Table9. Programming ModeDC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.5V± 0.25V)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP.
Table10. Programming ModeAC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V; VPP= 12.5V± 0.25V)
Note:1.VCC mustbe applied simultaneouslywithor beforeVPPand removed simultaneouslyorafterVPP. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0≤VIN≤VCC ±1 μA
ICC Supply Current 50 mA
IPP Program Current E=VIL 50 mA
VIL InputLow Voltage –0.3 0.8 V
VIH Input High Voltage 2.4 VCC+0.5 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –2.5mA 3.5 V
VID A9 Voltage 11.5 12.5 V
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Validto Chip Enable Low 2 μs
tQVEL tDS Input Validto Chip EnableLow 2 μs
tVPHAV tVPS VPP Highto Address Valid 2 μs
tVCHAV tVCS VCC Highto Address Valid 2 μs
tELEH tPW Chip Enable Program Pulse Width 45 55 μs
tEHQX tDH Chip Enable Highto Input Transition 2 μs
tQXGL tOES Input Transitionto Output EnableLow 2 μs
tGLQV tOE Output Enable Lowto Output Valid 120 ns
tGHQZ(2) tDFP Output Enable Highto Output Hi-Z 0 130 ns
tGHAX tAH Output Enable Highto Address
Transition 0ns

Partno	Mfg	Dc	Qty	Available	Descript
27C160	ST	N/a	3000	avai	16 Mbit 2Mb x8 or 1Mb x16 UV EPROM and OTP EPROM