27C1024 Fast Delivery |IC PHOENIX CO.,LIMITED

27C1024 ,1 Megabit (65 K x 16-Bit) CMOS EPROMLogic DiagramThe FDIP40W (window ceramic frit-seal package)has a transparent lid which allows the u ..
27C1024-10 , 1M-BIT [128K x 8/64K x 16] CMOS EPROM
27C1024-12 , 1M-BIT [128K x 8/64K x 16] CMOS EPROM
27C1024-15 , 1M-BIT [128K x 8/64K x 16] CMOS EPROM
27C1028 ,CMOS 1048576 BIT UV ERASABLE READ ONLY MEMORYapplications where program changes are frequently necessary. Once programmed, the device requires ..
27C128 , 64K(8K x 8) UV ERASABLE PROMs
2SA933 , EPITAXIAL PLANAR PNP SILICON TRANSISTORS
2SA933AS , General Purpose Transistor (50V, 0.15A)
2SA933AS TP Q , General Purpose Transistor
2SA933ASTPQ , General Purpose Transistor
2SA933ASTPR , General Purpose Transistor
2SA933S , EPITAXIAL PLANAR PNP SILICON TRANSISTORS

27C1024
1 Megabit (65 K x 16-Bit) CMOS EPROM
M27C1024 Mbit (64Kb x16) UV EPROM and OTP EPROM
September 1998 1/15
AI00702B
A0-A15
Q0-Q15PPVCC
M27C1024
VSS
Figure1. Logic Diagram± 10% SUPPLY VOLTAGEin READ
OPERATION
FASTACCESS TIME: 35ns
LOW POWER CONSUMPTION: Active Current 35mAat 5MHz Standby Current 100μA
PROGRAMMING VOLTAGE: 12.75V± 0.25V
PROGRAMMING TIME: 100μs/byte (typical)
ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 008Ch
DESCRIPTION
The M27C1024isa1 Mbit EPROM offeredinthe
two rangesUV (ultra violet erase) and OTP (one
time programmable).Itis ideally suitedfor micro-
processorsystemsrequiringlargedataor program
storage andis organizedas 65,536 wordsof16
bits.
The FDIP40W (window ceramic frit-seal package)
hasa transparentlid which allows the userto
exposethe chipto ultraviolet lightto erasethebit
pattern.A new pattern can thenbe writtentothe
deviceby followingthe programming procedure.
For application wherethe contentis programmed
only one time and erasureis not required, the
M27C1024is offeredin PDIP40, PLCC44 and
TSOP40(10x 14mm) packages.
A0-A15 Address Inputs
Q0-Q15 Data Outputs Chip Enable Output Enable Program
VPP Program Supply
VCC Supply Voltage
VSS Ground
Table1. SignalNames
FDIP40W(F)
PLCC44(C) TSOP40(N)x 14mm
PDIP40(B)
Q11
VSS
Q10
A12
A11
A10
A13
VSSQ1GE
Q12
VPP VCC
Q15
AI00703
M27C102420
Q14
Q13
A14
A15
Figure2A. DIPPin Connections
AI00704
A14
A11Q2 NC
Q12
VSS
Q11
Q10
A15
Q15
VSS
A12
Q13 NC
M27C1024
Q14
A13 A10Q7A1 PV
Figure2B. LCCPin Connections
Warning:NC=Not Connected.
DEVICE OPERATION
The modesof operationsof the M27C1024are
listedinthe OperatingModes table.Asingle power
supplyis requiredinthe read mode.All inputsare
TTL levels exceptfor Vpp and 12VonA9for
ElectronicSignature.
Read Mode
The M27C1024 has two control functions, bothof
which mustbe logically activein orderto obtain
dataatthe outputs. Chip Enable(E)isthe power
control and shouldbe usedfor device selection.
OutputEnable(G)isthe output control and should usedto gate datato the output pins, inde-
pendentof device selection. Assuming that the
addressesare stable,the address access time
(tAVQV)isequaltothe delayfrom Etooutput (tELQV).
Datais availableatthe output aftera delayoftOE
fromthe falling edgeofG, assuming thatE has
beenlow andthe addresses have been stablefor least tAVQV-tGLQV.
Standby Mode
The M27C1024 hasa standby mode whichre-
ducesthe active current from 35mAto 100μA.
The M27C1024is placedinthe standby modeby
applyinga TTLhigh signaltotheE input. Whenin
the standby mode, theoutputsareina high imped-
ance state, independentoftheG input.
Warning:NC=Not Connected.
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A11
A10
A15
DQ1
DQ0
DQ14
VPPCC
DQ15
AI01582
M27C1024
(Normal) 21SS
A12 A6
A13 A5
DQ12 DQ4
DQ11 DQ5
VSS
Figure2C. TSOPPin Connections
Warning:NC=Not Connected.
2/15
M27C1024
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40 to125 °C
TBIAS Temperature Under Bias –50 to125 °C
TSTG Storage Temperature –65 to150 °C
VIO(2) Inputor Output Voltages (exceptA9) –2to7 V
VCC Supply Voltage –2to7 V
VA9(2) A9 Voltage –2 to13.5 V
VPP Program Supply Voltage –2 to14 V
Notes:1. Exceptfor therating ”OperatingTemperature Range”, stresses above those listedin theTable ”Absolute Maximum Ratings”
may cause permanentdamageto thedevice. Theseare stress ratingsonlyand operationofthe deviceat theseorany other
conditions above those indicatedinthe Operatingsectionsofthis specificationis notimplied. Exposureto Absolute Maximum
Rating conditionsfor extendedperiodsmay affectdevice reliability.Referalsotothe STMicroelectronics SURE Programand other
relevant qualitydocuments. MinimumDC voltageonInputor Outputis –0.5Vwith possibleundershootto –2.0Vfor aperiodlessthan 20ns. MaximumDC
voltageon OutputisVCC +0.5Vwith possible overshoottoVCC+2Vfora periodlessthan 20ns. Dependson range.
Table2. Absolute MaximumRatings(1)
Mode E G P A9 VPP Q0- Q15
Read VIL VIL VIH XVCCorVSS Data Output
Output Disable VIL VIH XX VCCorVSS Hi-Z
Program VIL XVIL Pulse X VPP Data Input
Verify VIL VIL VIH XVPP Data Output
Program Inhibit VIH XX X VPP Hi-Z
Standby VIH XX X VCCorVSS Hi-Z
Electronic Signature VIL VIL VIH VID VCC Codes
Note:X=VIH orVIL,VID= 12V±0.5V
Table3. Operating Modes
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code VIL 0 0100 000 20h
Device Code VIH 1 0001 100 8Ch
Note: Outputs Q8-Q15aresetto’0’.
Table4. Electronic Signature
3/15
M27C1024
AI01822
High Speed
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure3.AC TestingInput Output Waveform
AI01823B
1.3V
OUTL= 30pF forHigh Speed= 100pFfor Standard includes JIGcapacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure4.AC Testing Load Circuit
High Speed Standard
Input RiseandFall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0to3V 0.4Vto 2.4V
Inputand Output TimingRef. Voltages 1.5V 0.8Vand2V
Table5. AC Measurement Conditions
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6 pF
COUT Output Capacitance VOUT =0V 12 pF
Note:1. Sampledonly,not 100%tested.
Table6. Capacitance(1) (TA =25°C,f=1 MHz)
Two Line Output Control
BecauseEPROMsare usuallyusedin largermem-
ory arrays, this product featuresa2 line control
function which accommodatesthe useof multiple
memory connection. The twoline control function
allows: the lowest possible memory power dissipation, complete assurance that output bus contention
willnot occur.
Forthe mostefficientuseof thesetwo controllines, shouldbe decoded and usedasthe primary
device selecting function,whileG shouldbe made common connectiontoall devicesinthe array
and connectedtothe READline fromthe system
control bus. This ensures thatall deselectedmem-
ory devicesarein their low power standby mode
and thatthe output pinsare only active when data required froma particular memory device.
System Considerations
The power switching characteristicsof Advanced
CMOSEPROMs require careful decouplingofthe
devices. The supply current, ICC, has three seg-
ments thatareof interesttothe system designer:
the standby current level,the active current level,
and transient current peaks thatare producedby
the fallingand rising edgesofE. Themagnitudeof
transientcurrentpeaks isdependentonthe capaci-
tive and inductive loadingof the deviceat the
output.
4/15
M27C1024
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤VIN≤VCC ±10 μA
ILO Output Leakage Current 0V≤ VOUT≤VCC ±10 μA
ICC Supply Current E=VIL,G=VIL,
IOUT= 0mA,f= 5MHz 35 mA
ICC1 Supply Current (Standby)TTL E=VIH 1mA
ICC2 Supply Current (Standby) CMOS E>VCC– 0.2V 100 μA
IPP Program Current VPP =VCC 100 μA
VIL Input Low Voltage –0.3 0.8 V
VIH(2) Input High Voltage 2 VCC+1 V
VOL OutputLow Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –400μA 2.4 V
Output High VoltageCMOS IOH= –100μAVCC–0.7 V
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslywithor afterVPP. MaximumDC voltageon OutputisVCC +0.5V.
Table7. Read ModeDC Characteristics(1)
(TA=0to70°C, –40to85°C; –40to 105°Cor –40to 125°C; VCC =5V±5%or5V± 10%;VPP =VCC)
Symbol Alt Parameter Test Condition
M27C1024
Unit-35(3) -45(3) -55(3)
Min Max Min Max Min Max
tAVQV tACC Address Validto Output Valid E= VIL,G=VIL 35 45 55 ns
tELQV tCE Chip EnableLowto Output Valid G=VIL 35 45 55 ns
tGLQV tOE Output EnableLowto Output Valid E=VIL 20 25 30 ns
tEHQZ(2) tDF Chip Enable Highto Output Hi-Z G=VIL 030 0 30 030 ns
tGHQZ(2) tDF Output Enable Highto Output Hi-Z E=VIL 030 0 30 030 ns
tAXQX tOH Address Transitionto Output
Transition E=VIL,G=VIL 000 ns
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslywithor afterVPP. Sampled only,not 100% tested. Speed obtainedwithHigh SpeedAC measurementconditions.
Table8A. ReadModeAC Characteristics(1)
(TA=0to70°C, –40to85°C; –40to 105°Cor –40to 125°C; VCC =5V±5%or5V± 10%;VPP =VCC)
5/15
M27C1024
Symbol Alt Parameter Test Condition
M27C1024
Unit-70 -80/-90 -10/-12/
-15/-20
Min Max Min Max Min Max
tAVQV tACC Address Validto Output Valid E= VIL,G=VIL 70 80 100 ns
tELQV tCE Chip EnableLowto Output Valid G=VIL 70 80 100 ns
tGLQV tOE Output EnableLowto Output Valid E=VIL 35 40 50 ns
tEHQZ(2) tDF Chip Enable Highto Output Hi-Z G=VIL 0 30 0 30 0 30 ns
tGHQZ(2) tDF Output Enable Highto Output Hi-Z E=VIL 0 30 0 30 0 30 ns
tAXQX tOH Address Transitionto Output
Transition E= VIL,G=VIL 000 ns
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslywithor afterVPP. Sampled only,not 100% tested.
Table8B. ReadModeAC Characteristics(1)
(TA=0to70°C, –40to85°C; –40to 105°Cor –40to 125°C; VCC =5V±5%or5V± 10%;VPP =VCC)
AI00705B
tAXQX
tEHQZ
A0-A15
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Figure5. Read ModeAC Waveforms
6/15
M27C1024
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0≤VIN≤VIH ±10 μA
ICC Supply Current 50 mA
IPP Program Current E=VIL 50 mA
VIL InputLow Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC+0.5 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High VoltageTTL IOH= –400μA 2.4 V
VID A9 Voltage 11.5 12.5 V
Note:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslywithor afterVPP.
Table9. ProgrammingModeDC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V;VPP= 12.75V± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVPL tAS Address Validto ProgramLow 2 μs
tQVPL tDS Input Validto ProgramLow 2 μs
tVPHPL tVPS VPP Highto ProgramLow 2 μs
tVCHPL tVCS VCC Highto ProgramLow 2 μs
tELPL tCES ChipEnable Lowto ProgramLow 2 μs
tPLPH tPW Program Pulse Width 95 105 μs
tPHQX tDH Program Highto Input Transition 2 μs
tQXGL tOES Input Transitionto Output Enable
Low 2 μs
tGLQV tOE Output EnableLowto Output Valid 100 ns
tGHQZ(2) tDFP Output Enable Highto OutputHi-Z 0 130 ns
tGHAX tAH Output Enable Highto Address
Transition 0ns
Notes:1.VCCmustbe applied simultaneouslywithor beforeVPPand removed simultaneouslywithor afterVPP. Sampled only,not 100% tested.
Table10. ProgrammingModeAC Characteristics(1)
(TA =25°C; VCC= 6.25V± 0.25V;VPP= 12.75V± 0.25V)
7/15
M27C1024
tAVPL
VALID
AI00706
A0-A15
Q0-Q15PP
VCC
DATAIN DATAOUT
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM VERIFY
Figure6. Programmingand Verify ModesAC Waveforms
The associated transient voltage peaks canbe
suppressedby complying withthe twoline output
control andby properly selected decouplingca-
pacitors.Itis recommendedthata 0.1μF ceramic
capacitorbe usedon every device between VCC
and VSS. Thisshouldbea highfrequencycapacitor low inherent inductance and shouldbe placed closetothe deviceas possible.In addition,a
4.7μF bulk electrolytic capacitor shouldbe used
betweenVcc andVSSfor every eight devices. The
bulk capacitor shouldbe located nearthe power
supply connection point. The purposeofthe bulk
capacitoristo overcomethe voltage drop causedthe inductive effectsof PCB traces.
Programming
Whendelivered (and aftereach’1’s erasureforUV
EPROM),all bitsofthe M27C1024areinthe’1’
state. Datais introducedby selectively program-
ming ’0’s intothe desiredbit locations. Although
only’0’swillbe programmed,both’1’s and’0’scan presentin the data word. The only wayto
changea’0’toa’1’isbydie exposureto ultraviolet
light (UV EPROM). The M27C1024isinthe pro-
gramming mode when VPP inputisat 12.75V,EisVIL andPis pulsedto VIL. The datatobe
programmedis appliedto16 bitsin paralleltothe
data output pins. The levels requiredforthead-
dress and data inputsare TTL. VCCis specifiedto 6.25V± 0.25V.
PRESTOII ProgrammingAlgorithm
PRESTOII Programming Algorithm allows pro-
grammingof the whole array witha guaranteed
margin,ina typical timeof6.5 seconds.Program-
ming with PRESTOII consistsof applyingase-
quenceof100μs programpulsestoeachworduntil correct verify occurs (see Figure7). During pro-
gramming and verify operation,a MARGIN MODE
circuitis automaticallyactivatedin orderto guaran-
tee that each cellis programmed with enough
margin. Nooverprogrampulseisapplied sincethe
verifyin MARGIN MODE provides necessarymar-
ginto each programmed cell.
DEVICE OPERATION (cont’d)
8/15
M27C1024

Partno	Mfg	Dc	Qty	Available	Descript
27C1024	ST	N/a	2900	avai	1 Megabit (65 K x 16-Bit) CMOS EPROM