Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset The SN74LVC112ADR is a dual negative-edge-triggered J-K flip-flop manufactured by Texas Instruments (TI). Below are its specifications, descriptions, and features based on Ic-phoenix technical data files:
### **Specifications:**
- **Manufacturer:** Texas Instruments (TI)
- **Type:** Dual Negative-Edge-Triggered J-K Flip-Flop
- **Logic Family:** LVC (Low-Voltage CMOS)
- **Supply Voltage Range:** **1.65V to 3.6V**
- **High-Speed Operation:** **5.5 ns at 3.3V**
- **Input Voltage Range:** **0V to 5.5V** (tolerant)
- **Output Drive Capability:** **±24 mA at 3.3V**
- **Operating Temperature Range:** **-40°C to +85°C**
- **Package Type:** **SOIC-16**
### **Descriptions:**
- The SN74LVC112ADR features two independent J-K flip-flops with **clear (CLR)** and **preset (PRE)** inputs.
- It operates on a **negative-edge-triggered clock (CLK)**, meaning the state changes occur on the falling edge of the clock signal.
- Supports **partial power-down mode** with I/O protection, allowing inputs to exceed the supply voltage.
- Designed for **high-speed, low-power** applications in **3.3V and mixed-voltage systems**.
### **Features:**
- **Wide Operating Voltage Range:** 1.65V to 3.6V
- **5V-Tolerant Inputs/Outputs** (allowing interfacing with 5V logic)
- **Low Power Consumption:** Typical **ICC** of **10 µA**
- **Schmitt-Trigger Inputs** for improved noise immunity
- **Latch-Up Performance Exceeds 250 mA per JESD 17**
- **ESD Protection Exceeds JESD 22:**
- 2000V Human-Body Model (HBM)
- 1000V Charged-Device Model (CDM)
This information is strictly factual, sourced from TI's official documentation. Let me know if you need further details.
