Dual PLLs for 46/49 MHz Cordless Telephones# Technical Documentation: MC145166P Programmable Dual-Modulus Prescaler
## 1. Application Scenarios
### 1.1 Typical Use Cases
The MC145166P is a programmable dual-modulus prescaler primarily employed in phase-locked loop (PLL) frequency synthesizers . Its core function is to divide a high-frequency VCO (Voltage-Controlled Oscillator) output signal by a programmable integer value, enabling precise frequency generation in RF and communication systems.
Primary operational modes:
- Dual-modulus division : Operates with selectable divide ratios (e.g., 64/65, 128/129) controlled by a modulus control pin.
- Programmable reference divider : Often used in conjunction with a programmable counter to achieve wide division ranges without sacrificing channel resolution.
- Frequency translation : Bridges high-frequency VCO signals (up to several hundred MHz, depending on the specific variant and technology) to lower frequencies processable by standard CMOS PLL ICs.
### 1.2 Industry Applications
- Two-Way Land Mobile Radios : For channel selection in VHF/UHF bands.
- Cellular Infrastructure (Early Systems) : In base station and mobile unit synthesizers.
- Wireless Data Links : For fixed-frequency or frequency-hopping systems.
- Test and Measurement Equipment : As part of signal generator or frequency counter circuits.
- Broadcast Equipment : In FM transmitters or receiver local oscillators.
- Satellite Communication Terminals : For L-band frequency synthesis.
### 1.3 Practical Advantages and Limitations
Advantages:
- Extended Frequency Range : Allows standard CMOS PLL chips (often limited to ~10-20 MHz) to control VCOs operating in the VHF/UHF range.
- Improved Phase Noise : When properly implemented, the dual-modulus architecture minimizes the division ratio, which can reduce phase noise degradation compared to a fixed high-division-ratio prescaler.
- CMOS Compatibility : Operates from a single +5V supply, interfacing directly with other CMOS logic and microcontrollers.
- Programmability : Enables flexible frequency step sizes and agile frequency switching.
Limitations:
- Switching Speed : The dual-modulus operation involves toggling between two divide ratios. The settling time during modulus changes can limit the frequency switching speed of the overall PLL.
- Power Consumption : While CMOS, operating at high RF input frequencies can lead to higher current draw.
- Input Sensitivity : Requires careful attention to input signal level and waveform to ensure reliable counting at the maximum specified frequency. Performance degrades near the upper frequency limit.
- Spurious Signals : Improper board layout or power supply decoupling can lead to spurious outputs or increased phase noise.
- Aging Technology : As a part from the early CMOS era, its maximum frequency (typically up to 200 MHz for the 'P' suffix in standard commercial temperature range) is low by modern standards. Newer silicon or GaAs prescalers offer much higher operating frequencies.
## 2. Design Considerations
### 2.1 Common Design Pitfalls and Solutions
- Pitfall 1: Input Signal Integrity
- Problem : Insufficient input signal amplitude or improper DC bias causes erratic counting or complete failure at high frequencies.
- Solution : Use an RF amplifier/buffer stage (e.g., a transistor or dedicated RF amplifier IC) to ensure the input signal meets the required sensitivity (typically specified as a minimum mVpp into a specific impedance). Implement proper AC coupling and bias networks as per the datasheet.
- Pitfall 2: Modulus Control Timing
- Problem : The `Modulus Control` input must be stable during specific phases of the internal counter cycle. Violating setup/hold times causes incorrect division ratios.
