LVDS 24-Bit Color Flat Panel Display (FPD) Link# DS90CR583MTD Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS90CR583MTD from National Semiconductor (NS) is a 28-bit Channel Link II serializer specifically designed for high-speed digital video and data transmission applications. This component converts 28 bits of single-ended LVCMOS/LVTTL data into a single LVDS serial data stream, making it ideal for:
- Digital Display Interfaces : Primary application in LCD/OLED display systems for transmitting RGB data, control signals, and timing information from timing controllers to panel column drivers
- Camera Systems : High-resolution digital camera interfaces requiring robust long-distance data transmission
- Medical Imaging Equipment : Digital X-ray systems and ultrasound machines where high-speed, low-noise data transmission is critical
- Industrial Automation : Machine vision systems and industrial control panels requiring reliable video/data transmission in electrically noisy environments
### Industry Applications
- Consumer Electronics : High-definition televisions, digital signage, and professional monitors
- Automotive Infotainment : Center console displays and digital instrument clusters
- Avionics : Cockpit displays and in-flight entertainment systems
- Medical Devices : Patient monitoring displays and diagnostic equipment interfaces
### Practical Advantages and Limitations
Advantages:
- Reduced EMI : LVDS signaling significantly reduces electromagnetic interference compared to parallel interfaces
- Cable Reduction : Transmits 28 data lines plus clock over only 4 differential pairs (3 data + 1 clock)
- High Speed : Supports pixel clock rates up to 85 MHz, enabling resolutions up to UXGA (1600×1200)
- Low Power : Typical power consumption of 150mW at 3.3V supply
- Robust Operation : Built-in fail-safe features ensure predictable behavior during power-up/down sequences
Limitations:
- Fixed Configuration : Limited to specific data mapping; not programmable for different interface protocols
- Distance Constraints : Maximum reliable transmission distance of approximately 10 meters with proper cabling
- Clock Dependency : Requires precise clock timing; sensitive to clock jitter and skew
- Component Matching : Requires complementary deserializer (DS90CR584) for complete system implementation
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Decoupling
- Pitfall : Inadequate decoupling causing signal integrity issues and increased jitter
- Solution : Use 0.1μF ceramic capacitors placed within 5mm of each power pin, plus 10μF bulk capacitor per power rail
Clock Signal Integrity
- Pitfall : Poor clock quality leading to desynchronization at receiver
- Solution : Implement proper clock tree design with controlled impedance, minimal vias, and equal trace lengths
LVDS Termination
- Pitfall : Incorrect termination causing signal reflections and data errors
- Solution : Use 100Ω differential termination resistors at the receiver end, placed close to deserializer inputs
### Compatibility Issues
Voltage Level Mismatch
- The serializer operates with 3.3V LVCMOS/LVTTL inputs but requires careful consideration when interfacing with 5V or 1.8V components
- Solution : Use level shifters or voltage dividers for incompatible voltage domains
Timing Constraints
- Maximum pixel clock frequency of 85MHz may not support ultra-high-resolution displays
- Compatible Deserializer : Must pair with DS90CR584 for proper system operation
- Backward Compatibility : Not compatible with first-generation Channel Link devices
### PCB Layout Recommendations
Power Distribution
- Use separate power planes for analog and digital sections
- Implement star-point grounding near the device
- Ensure adequate power plane capacitance for transient current demands
Signal Routing
- LVDS Pairs : Route
